loadpatents
name:-0.011963844299316
name:-0.023914813995361
name:-0.00049495697021484
Pan; James N. Patent Filings

Pan; James N.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Pan; James N..The latest application filed is for "strain enhanced semiconductor devices and methods for their fabrication".

Company Profile
0.21.9
  • Pan; James N. - Hanover MD
  • Pan; James N. - Hopewell Junction NY
  • Pan; James N. - West Jordan UT
  • Pan; James N. - Fishkill NY
  • Pan; James N. - Santa Clara CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Magnetic dynamic random access nonvolatile semiconductor memory (MRAM)
Grant 8,933,519 - Pan January 13, 2
2015-01-13
Replacement metal gate transistors with reduced gate oxide leakage
Grant 8,753,943 - Pan , et al. June 17, 2
2014-06-17
Strain enhanced semiconductor devices and methods for their fabrication
Grant 8,124,473 - Pan , et al. February 28, 2
2012-02-28
Shallow trench isolation process and structure with minimized strained silicon consumption
Grant 7,732,336 - Xiang , et al. June 8, 2
2010-06-08
Shallow trench isolation process and structure with minimized strained silicon consumption
Grant 7,462,549 - Xiang , et al. December 9, 2
2008-12-09
Strain Enhanced Semiconductor Devices And Methods For Their Fabrication
App 20080251851 - PAN; James N. ;   et al.
2008-10-16
Shallow Trench Isolation Process And Structure With Minimized Strained Silicon Consumption
App 20080213952 - Xiang; Qi ;   et al.
2008-09-04
Low-power multiple-channel fully depleted quantum well CMOSFETs
Grant 7,253,484 - Pan , et al. August 7, 2
2007-08-07
Low-power multiple-channel fully depleted quantum well CMOSFETs
App 20060278938 - Pan; James N. ;   et al.
2006-12-14
Method of fabricating an integrated circuit channel region
Grant 7,138,302 - Xiang , et al. November 21, 2
2006-11-21
Formation of finFET using a sidewall epitaxial layer
Grant 7,078,299 - Maszara , et al. July 18, 2
2006-07-18
Low-power multiple-channel fully depleted quantum well CMOSFETs
Grant 7,074,657 - Pan , et al. July 11, 2
2006-07-11
Method for determining metal work function by formation of Schottky diodes with shadow mask
Grant 7,045,384 - Pan , et al. May 16, 2
2006-05-16
Engineered metal gate electrode
Grant 7,033,888 - Pan , et al. April 25, 2
2006-04-25
Strained silicon semiconductor on insulator MOSFET
Grant 7,033,869 - Xiang , et al. April 25, 2
2006-04-25
Method of growing as a channel region to reduce source/drain junction capacitance
Grant 6,955,969 - Djomehri , et al. October 18, 2
2005-10-18
Semiconductor on insulator MOSFET having strained silicon channel
Grant 6,943,087 - Xiang , et al. September 13, 2
2005-09-13
Replacement gate strained silicon finFET process
Grant 6,936,516 - Goo , et al. August 30, 2
2005-08-30
Strained silicon MOSFETs having NMOS gates with work functions for compensating NMOS threshold voltage shift
Grant 6,929,992 - Djomehri , et al. August 16, 2
2005-08-16
Shallow trench isolation process and structure with minimized strained silicon consumption
App 20050151222 - Xiang, Qi ;   et al.
2005-07-14
Method of fabricating a strained silicon channel FinFET
App 20050153486 - Xiang, Qi ;   et al.
2005-07-14
Strained silicon MOSFETs having improved thermal dissipation
Grant 6,900,143 - Pan , et al. May 31, 2
2005-05-31
Low-power multiple-channel fully depleted quantum well CMOSFETs
App 20050104140 - Pan, James N. ;   et al.
2005-05-19
One step deposition method for high-k dielectric and metal gate electrode
Grant 6,893,910 - Woo , et al. May 17, 2
2005-05-17
Method of growing as a channel region to reduce source/drain junction capicitance
App 20050048743 - Djomehri, Ihsan J. ;   et al.
2005-03-03
Formation Of Finfet Using A Sidewall Epitaxial Layer
App 20050048727 - Maszara, Witold P. ;   et al.
2005-03-03
Methods for fabricating CMOS-compatible lateral bipolar junction transistors
Grant 6,861,325 - Pan , et al. March 1, 2
2005-03-01
Self aligned double gate transistor having a strained channel region and process therefor
Grant 6,855,982 - Xiang , et al. February 15, 2
2005-02-15
Engineered metal gate electrode
App 20040175910 - Pan, James N. ;   et al.
2004-09-09
Engineered metal gate electrode
Grant 6,727,560 - Pan , et al. April 27, 2
2004-04-27

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed