Palumbo; Elisabetta

Patent Applications and Registrations

Patent applications and USPTO patent grants for Palumbo; Elisabetta.The latest application filed is for "reading voltage generator for a non-volatile eeprom memory cell matrix of a semiconductor device and corresponding manufacturing process".

Company Profile

0.7.7

Palumbo; Elisabetta - Bernareggio IT
Palumbo; Elisabetta - Milano IT
Palumbo; Elisabetta - Milan IT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Reading voltage generator for a non-volatile EEPROM memory cell matrix of a semiconductor device and corresponding manufacturing process Grant 7,663,927 - Palumbo , et al. February 16, 2	2010-02-16
Process for manufacturing a byte selection transistor for a matrix of non volatile memory cells and corresponding structure Grant 7,456,467 - Zuliani , et al. November 25, 2	2008-11-25
Reading Voltage Generator For A Non-volatile Eeprom Memory Cell Matrix Of A Semiconductor Device And Corresponding Manufacturing Process App 20080123404 - Palumbo; Elisabetta ; et al.	2008-05-29
Process for manufacturing a byte selection transistor for a matrix of non volatile memory cells and corresponding structure App 20060043461 - Zuliani; Paola ; et al.	2006-03-02
Process for manufacturing a byte selection transistor for a matrix of non volatile memory cells and corresponding structure Grant 6,972,454 - Zuliani , et al. December 6, 2	2005-12-06
Process for manufacturing a byte selection transistor for a matrix of non volatile memory cells and corresponding structure App 20040152267 - Zuliani, Paola ; et al.	2004-08-05
Method of manufacturing an integrated circuit, for integrating an electrically programmable, non-volatile memory and high-performance logic circuitry in the same semiconductor chip Grant 6,627,928 - Peschiaroli , et al. September 30, 2	2003-09-30
Lateral DMOS transistor with first and second drain electrodes in respective contact with high-and low-concentration portions of a drain region Grant 6,624,471 - Zatelli , et al. September 23, 2	2003-09-23
Method of manufacturing an integrated circuit, for integrating an electrically programmable, non-volatile memory and high-performance logic circuitry in the same semiconductor chip App 20030032244 - Peschiaroli, Daniela ; et al.	2003-02-13
Method of manufacturing an electrically programmable, non-volatile memory and high-performance logic circuitry in the same semiconductor chip Grant 6,482,698 - Peschiaroli , et al. November 19, 2	2002-11-19
Lateral DMOS transistor App 20020040995 - Zatelli, Nicola ; et al.	2002-04-11
Method of manufacturing an electrically programmable, non-volatile memory and high-performance logic circuitry in the same semiconductor chip App 20010049166 - Peschiaroli, Daniela ; et al.	2001-12-06
Process for the fabrication of an integrated circuit comprising MOS transistors for low voltage, EPROM cells and MOS transistors for high voltage Grant 6,319,780 - Crivelli , et al. November 20, 2	2001-11-20
Process for the fabrication of an integrated circuit comprising MOS transistors for low voltage, EPROM cells and MOS transistors for high voltage App 20010018250 - Crivelli, Barbara ; et al.	2001-08-30

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