Paluch, Edward J.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Paluch, Edward J..The latest application filed is for "time sliced architecture for graphics display system".
- Paluch, Edward J. - Santa Clara CA
| Patent | Date |
|---|---|
| Time sliced architecture for graphics display system App 20050270297 - Munday, Tarjinder Singh ; et al. | 2005-12-08 |
| Asynchronous memory interface for a video processor with a 2N sized buffer and N+1 wide bit gray coded counters Grant 6,457,114 - Paluch September 24, 2 | 2002-09-24 |
| Motion compensated digital video decoding with buffered picture storage memory map Grant 6,088,047 - Bose , et al. July 11, 2 | 2000-07-11 |
| Bank arbitration for SDRAM memory control Grant 5,987,574 - Paluch November 16, 1 | 1999-11-16 |
| Asynchronous memory interface for a video processor with a 2.sup.N sized buffer and N+1 bit wide gray coded counters Grant 5,960,468 - Paluch September 28, 1 | 1999-09-28 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.
| 