loadpatents
name:-0.040655136108398
name:-0.026154041290283
name:-0.024134874343872
Pal; Supratim Patent Filings

Pal; Supratim

Patent Applications and Registrations

Patent applications and USPTO patent grants for Pal; Supratim.The latest application filed is for "compiler assisted register file write reduction".

Company Profile
21.23.37
  • Pal; Supratim - Bangalore IN
  • PAL; Supratim - Folsom CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Sparse matrix optimization mechanism
Grant 11,443,407 - Sharma , et al. September 13, 2
2022-09-13
Compiler Assisted Register File Write Reduction
App 20220261949 - GURRAM; Chandra S. ;   et al.
2022-08-18
Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format
Grant 11,361,496 - Maiyuran , et al. June 14, 2
2022-06-14
Scalable Sparse Matrix Multiply Acceleration Using Systolic Arrays With Feedback Inputs
App 20220156343 - MAIYURAN; SUBRAMANIAM ;   et al.
2022-05-19
Use Of A Single Instruction Set Architecture (isa) Instruction For Vector Normalization
App 20220147316 - Rhisheekesan; Abhishek ;   et al.
2022-05-12
Compiler assisted register file write reduction
Grant 11,321,799 - Gurram , et al. May 3, 2
2022-05-03
Graphics Processors And Graphics Processing Units Having Dot Product Accumulate Instruction For Hybrid Floating Point Format
App 20220129266 - Maiyuran; Subramaniam ;   et al.
2022-04-28
Instructions and logic for vector multiply add with zero skipping
Grant 11,314,515 - Pal , et al. April 26, 2
2022-04-26
Sparse Matrix Optimization Mechanism
App 20220092723 - Sharma; Namita ;   et al.
2022-03-24
Computing Efficient Cross Channel Operations In Parallel Computing Machines Using Systolic Arrays
App 20220058158 - Maiyuran; Subramaniam ;   et al.
2022-02-24
Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs
Grant 11,204,977 - Maiyuran , et al. December 21, 2
2021-12-21
Computing Efficient Cross Channel Operations In Parallel Computing Machines Using Systolic Arrays
App 20210365402 - Maiyuran; Subramaniam ;   et al.
2021-11-25
Computing efficient cross channel operations in parallel computing machines using systolic arrays
Grant 11,182,337 - Maiyuran , et al. November 23, 2
2021-11-23
Scalable Sparse Matrix Multiply Acceleration Using Systolic Arrays With Feedback Inputs
App 20210349966 - MAIYURAN; SUBRAMANIAM ;   et al.
2021-11-11
Hierarchical General Register File (grf) For Execution Block
App 20210349715 - Appu; Abhishek R. ;   et al.
2021-11-11
Compaction Of Diverged Lanes For Efficient Use Of Alus
App 20210349717 - Gurram; Chandra ;   et al.
2021-11-11
Use of a single instruction set architecture (ISA) instruction for vector normalization
Grant 11,157,238 - Rhisheekesan , et al. October 26, 2
2021-10-26
Graphics Processors And Graphics Processing Units Having Dot Product Accumulate Instruction For Hybrid Floating Point Format
App 20210312697 - Maiyuran; Subramaniam ;   et al.
2021-10-07
Instruction And Logic For Systolic Dot Product With Accumulate
App 20210303299 - MAIYURAN; SUBRAMANIAM ;   et al.
2021-09-30
Sparse matrix optimization mechanism
Grant 11,127,108 - Sharma , et al. September 21, 2
2021-09-21
Control Flow Mechanism For Execution Of Graphics Processor Instructions Using Active Channel Packing
App 20210286626 - Maiyuran; Subramaniam M. ;   et al.
2021-09-16
Compiler Assisted Register File Write Reduction
App 20210192673 - GURRAM; Chandra S. ;   et al.
2021-06-24
Instructions And Logic For Vector Multiply Add With Zero Skipping
App 20210191724 - Pal; Supratim ;   et al.
2021-06-24
Instruction and logic for systolic dot product with accumulate
Grant 11,042,370 - Maiyuran , et al. June 22, 2
2021-06-22
Sparse Matrix Optimization Mechanism
App 20210183002 - Sharma; Namita ;   et al.
2021-06-17
Use Of A Single Instruction Set Architecture (isa) Instruction For Vector Normalization
App 20210149635 - Rhisheekesan; Abhishek ;   et al.
2021-05-20
Hierarchical general register file (GRF) for execution block
Grant 11,010,163 - Appu , et al. May 18, 2
2021-05-18
Control flow mechanism for execution of graphics processor instructions using active channel packing
Grant 10,990,409 - Maiyuran , et al. April 27, 2
2021-04-27
Register sharing mechanism
Grant 10,983,794 - Lueh , et al. April 20, 2
2021-04-20
Deep Learning Implementations Using Systolic Arrays And Fused Operations
App 20210089316 - RASH; William ;   et al.
2021-03-25
Utilizing Structured Sparsity In Systolic Arrays
App 20210081201 - Maiyuran; Subramaniam ;   et al.
2021-03-18
Register Sharing Mechanism
App 20200394041 - Lueh; Guei-Yuan ;   et al.
2020-12-17
Accumulator pooling mechanism
Grant 10,839,478 - Lueh , et al. November 17, 2
2020-11-17
Accumulator Pooling Mechanism
App 20200320662 - Lueh; Guei-Yuan ;   et al.
2020-10-08
Dynamic thread splitting having multiple instruction pointers for the same thread
Grant 10,789,071 - Nalluri , et al. September 29, 2
2020-09-29
Register Sharing Mechanism
App 20200285471 - ASHAR; PRATIK J. ;   et al.
2020-09-10
Recompiling GPU code based on spill/fill instructions and number of stall cycles
Grant 10,698,689 - Ashar , et al.
2020-06-30
Software scoreboard information and synchronization
Grant 10,692,170 - Maiyuran , et al.
2020-06-23
Register Sharing Mechanism
App 20200073664 - ASHAR; PRATIK J. ;   et al.
2020-03-05
Hierarchical General Register File (grf) For Execution Block
App 20200026514 - Appu; Abhishek R. ;   et al.
2020-01-23
Software Scoreboard Information And Synchronization
App 20190362460 - Maiyuran; Subramaniam ;   et al.
2019-11-28
Instruction And Logic For Systolic Dot Product With Accumulate
App 20190324746 - MAIYURAN; SUBRAMANIAM ;   et al.
2019-10-24
Hierarchical general register file (GRF) for execution block
Grant 10,423,415 - Appu , et al. Sept
2019-09-24
Fusion of SIMD Processing Units
App 20190265973 - Maiyuran; Subramaniam ;   et al.
2019-08-29
Software scoreboard information and synchronization
Grant 10,360,654 - Maiyuran , et al.
2019-07-23
Source operand read suppression for graphics processors
Grant 10,152,452 - Pal , et al. Dec
2018-12-11
Graphics Control Flow Mechanism
App 20180307487 - Maiyuran; Subramaniam M. ;   et al.
2018-10-25
Hierarchical General Register File (grf) For Execution Block
App 20180285106 - Appu; Abhishek R. ;   et al.
2018-10-04
Instruction that performs a scatter write
Grant 9,880,839 - Chen , et al. January 30, 2
2018-01-30
Banked memory access efficiency by a graphics processor
Grant 9,632,801 - Pal , et al. April 25, 2
2017-04-25
Dynamic Thread Splitting
App 20170010894 - Nalluri; Hema C. ;   et al.
2017-01-12
Source Operand Read Suppression For Graphics Processors
App 20160350112 - PAL; SUPRATIM ;   et al.
2016-12-01
Simplification of local contrast compensation by using weighted look-up table
Grant 9,245,495 - Gupta , et al. January 26, 2
2016-01-26
Instruction That Performs A Scatter Write
App 20150309800 - CHEN; WEI-YU ;   et al.
2015-10-29
Banked Memory Access Efficiency By A Graphics Processor
App 20150294435 - Pal; Supratim ;   et al.
2015-10-15
Simplification Of Local Contrast Compensation By Using Weighted Look-up Table
App 20140313243 - Gupta; Niraj ;   et al.
2014-10-23

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