Pal; Subhasis Patent Filings

Patent	Date
Method of and system for physically distributed, logically shared, and data slice-synchronized shared memory switching App 20070121499 - Pal; Subhasis ; et al.	2007-05-31
Method of scalable non-blocking shared memory output-buffered switching of variable length data packets from pluralities of ports at full line rate, and apparatus therefor Grant 6,999,464 - Wang , et al. February 14, 2	2006-02-14
Method of addressing sequential data packets from a plurality of input data line cards for shared memory storage and the like, and novel address generator therefor Grant 6,684,317 - Wang , et al. January 27, 2	2004-01-27
Method of addressing sequential data packets from a plurality of input data line cards for shared memory storage and the like, and novel address generator therefor App 20030120894 - Wang, Xiaolin ; et al.	2003-06-26
Method of scalable non-blocking shared memory output-buffered switching of variable length data packets from pluralities of ports at full line rate, and apparatus therefor App 20030043828 - Wang, Xiaolin ; et al.	2003-03-06
System for interposing a multi-port internally cached DRAM in a control path for temporarily storing multicast start of packet data until such can be passed Grant 6,272,567 - Pal , et al. August 7, 2	2001-08-07
Method of and operating architectural enhancement for multi-port internally cached dynamic random access memory (AMPIC DRAM) systems, eliminating external control paths and random memory addressing, while providing zero bus contention for DRAM access Grant 6,138,219 - Soman , et al. October 24, 2	2000-10-24

Patent

Date

Method of and system for physically distributed, logically shared, and data slice-synchronized shared memory switching
App 20070121499 - Pal; Subhasis ; et al.

2007-05-31

Method of scalable non-blocking shared memory output-buffered switching of variable length data packets from pluralities of ports at full line rate, and apparatus therefor
Grant 6,999,464 - Wang , et al. February 14, 2

2006-02-14

Method of addressing sequential data packets from a plurality of input data line cards for shared memory storage and the like, and novel address generator therefor
Grant 6,684,317 - Wang , et al. January 27, 2

2004-01-27

Method of addressing sequential data packets from a plurality of input data line cards for shared memory storage and the like, and novel address generator therefor
App 20030120894 - Wang, Xiaolin ; et al.

2003-06-26

Method of scalable non-blocking shared memory output-buffered switching of variable length data packets from pluralities of ports at full line rate, and apparatus therefor
App 20030043828 - Wang, Xiaolin ; et al.

2003-03-06

System for interposing a multi-port internally cached DRAM in a control path for temporarily storing multicast start of packet data until such can be passed
Grant 6,272,567 - Pal , et al. August 7, 2

2001-08-07

Method of and operating architectural enhancement for multi-port internally cached dynamic random access memory (AMPIC DRAM) systems, eliminating external control paths and random memory addressing, while providing zero bus contention for DRAM access
Grant 6,138,219 - Soman , et al. October 24, 2

2000-10-24

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Pal; Subhasis

Patent Applications and Registrations