loadpatents
name:-0.056953191757202
name:-0.047625064849854
name:-0.015031099319458
PAI; Yi-Fang Patent Filings

PAI; Yi-Fang

Patent Applications and Registrations

Patent applications and USPTO patent grants for PAI; Yi-Fang.The latest application filed is for "method for manufacturing semiconductor structure with enlarged volumes of source-drain regions".

Company Profile
11.30.31
  • PAI; Yi-Fang - Hsinchu TW
  • PAI; Yi-Fang - Hsinchu City TW
  • Pai; Yi-Fang - Hsin-Chu N/A TW
  • - Hsinchu TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method For Manufacturing Semiconductor Structure With Enlarged Volumes Of Source-drain Regions
App 20220293773 - YANG; Tsung-Hsi ;   et al.
2022-09-15
Integrated Circuits Having Source/drain Structure And Method Of Making
App 20220285157 - HUANG; Shih-Hsien ;   et al.
2022-09-08
Source/Drain Regions of Semiconductor Devices and Methods of Forming the Same
App 20220231019 - Lu; Wei Hao ;   et al.
2022-07-21
Integrated circuits having source/drain structure and method of making
Grant 11,373,867 - Huang , et al. June 28, 2
2022-06-28
Source/drain regions of semiconductor devices and methods of forming the same
Grant 11,296,080 - Lu , et al. April 5, 2
2022-04-05
Epitaxy Regions with Large Landing Areas for Contact Plugs
App 20220028856 - Tai; Jung-Chi ;   et al.
2022-01-27
Semiconductor Device and Methods of Forming Thereof
App 20210391324 - Lu; Wei Hao ;   et al.
2021-12-16
Semiconductor device source/drain region with arsenic-containing barrier region
Grant 10,861,935 - Kuo , et al. December 8, 2
2020-12-08
Integrated Circuits Having Source/drain Structure And Method Of Making
App 20200350432 - HUANG; Shih-Hsien ;   et al.
2020-11-05
Integrated circuits having source/drain structure
Grant 10,734,517 - Huang , et al.
2020-08-04
Semiconductor Device Source/Drain Region with Arsenic-Containing Barrier Region
App 20190355816 - Kuo; Chien-I ;   et al.
2019-11-21
Semiconductor device source/drain region with arsenic-containing barrier region
Grant 10,374,038 - Kuo , et al.
2019-08-06
Semiconductor device structure and method for forming the same
Grant 10,340,190 - Lu , et al.
2019-07-02
Semiconductor Device Source/drain Region With Arsenic-containing Barrier Region
App 20190165100 - KUO; Chien-I ;   et al.
2019-05-30
Semiconductor Device Structure And Method For Forming The Same
App 20190164835 - LU; Wei-Hao ;   et al.
2019-05-30
Cyclic deposition etch chemical vapor deposition epitaxy to reduce EPI abnormality
Grant 10,134,896 - Tsai , et al. November 20, 2
2018-11-20
Methods for reducing contact resistance in semiconductors manufacturing process
Grant 9,997,631 - Yang , et al. June 12, 2
2018-06-12
Integrated Circuits Having Source/drain Structure
App 20180033887 - HUANG; Shih-Hsien ;   et al.
2018-02-01
Methods For Reducing Contact Resistance In Semiconductor Manufacturing Process
App 20170352762 - YANG; Cheng-Yu ;   et al.
2017-12-07
Integrated circuits having source/drain structure
Grant 9,786,780 - Huang , et al. October 10, 2
2017-10-10
Epitaxy profile engineering for FinFETs
Grant 9,666,691 - Su , et al. May 30, 2
2017-05-30
Semiconductor structure with enhanced contact and method of manufacture the same
Grant 9,647,115 - Okuno , et al. May 9, 2
2017-05-09
Semiconductor Structure With Enhanced Contact And Method Of Manufacture The Same
App 20170110578 - OKUNO; Yasutoshi ;   et al.
2017-04-20
Method of fabricating an integrated circuit device
Grant 9,564,509 - Yeh , et al. February 7, 2
2017-02-07
Source/drain formation and structure
Grant 9,537,004 - Wu , et al. January 3, 2
2017-01-03
Epitaxial formation of source and drain regions
Grant 9,443,847 - Tsai , et al. September 13, 2
2016-09-13
Method for incorporating impurity element in EPI silicon process
Grant 9,356,150 - Su , et al. May 31, 2
2016-05-31
Method For Incorporating Impurity Element In Epi Silicon Process
App 20150364604 - Su; Chien-Chang ;   et al.
2015-12-17
Device with Engineered Epitaxial Region and Methods of Making Same
App 20150364602 - Wong; King-Yuen ;   et al.
2015-12-17
Device with engineered epitaxial region and methods of making same
Grant 9,117,843 - Wong , et al. August 25, 2
2015-08-25
Method for incorporating impurity element in EPI silicon process
Grant 9,117,905 - Su , et al. August 25, 2
2015-08-25
Epitaxial Formation Of Source And Drain Regions
App 20150214223 - TSAI; Chun Hsiung ;   et al.
2015-07-30
Method Of Fabricating An Integrated Circuit Device
App 20150118807 - YEH; Ming-Hsi ;   et al.
2015-04-30
Epitaxial formation of source and drain regions
Grant 9,012,310 - Tsai , et al. April 21, 2
2015-04-21
Method of fabricating an integrated circuit device
Grant 08921177 -
2014-12-30
Method of fabricating an integrated circuit device
Grant 8,921,177 - Yeh , et al. December 30, 2
2014-12-30
Asymmetric cyclic desposition etch epitaxy
Grant 8,906,789 - Tsai , et al. December 9, 2
2014-12-09
Integrated Circuits Having Source/drain Structure
App 20140299945 - HUANG; Shih-Hsien ;   et al.
2014-10-09
Asymmetric Cyclic Desposition Etch Epitaxy
App 20140264348 - Tsai; Chun Hsiung ;   et al.
2014-09-18
Cyclic Deposition Etch Chemical Vapor Deposition Epitaxy To Reduce Epi Abnormality
App 20140246710 - TSAI; Chun Hsiung ;   et al.
2014-09-04
Integrated circuits and fabrication methods thereof
Grant 8,778,767 - Huang , et al. July 15, 2
2014-07-15
Epitaxial Formation Of Source And Drain Regions
App 20130328126 - TSAI; Chun Hsiung ;   et al.
2013-12-12
Device with Engineered Epitaxial Region and Methods of Making Same
App 20130062670 - Wong; King-Yuen ;   et al.
2013-03-14
Method Of Fabricating An Integrated Circuit Device
App 20130023094 - YEH; Ming-Hsi ;   et al.
2013-01-24
Epitaxy Profile Engineering for FinFETs
App 20130001705 - Su; Chien-Chang ;   et al.
2013-01-03
Method of forming strained structures with compound profiles in semiconductor devices
Grant 8,343,872 - Sung , et al. January 1, 2
2013-01-01
Source/Drain Formation and Structure
App 20120299121 - Wu; Chii-Ming ;   et al.
2012-11-29
Epitaxy profile engineering for FinFETs
Grant 8,263,451 - Su , et al. September 11, 2
2012-09-11
Integrated Circuits And Fabrication Methods Thereof
App 20120126296 - HUANG; Shih-Hsien ;   et al.
2012-05-24
Epitaxy Profile Engineering for FinFETs
App 20110210404 - Su; Chien-Chang ;   et al.
2011-09-01
Method For Incorporating Impurity Element In Epi Silicon Process
App 20110147846 - Su; Chien-Chang ;   et al.
2011-06-23
Method Of Forming Strained Structures In Semiconductor Devices
App 20110108894 - Sung; Hsueh-Chang ;   et al.
2011-05-12

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