Pai; Deepak K.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Pai; Deepak K..The latest application filed is for "integrated circuits having lead contacts and leadless contact pads connected to a surface of a printed wiring board, and methods for connecting the same".

Company Profile

0.24.13

Pai; Deepak K. - Burnsville MN US
Pai; Deepak K. - Bumsville MN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method of connecting a grid array package to a printed circuit board Grant 8,549,737 - Pai October 8, 2	2013-10-08
Low profile compliant leads Grant 8,481,862 - Pai , et al. July 9, 2	2013-07-09
Method for manufacturing leads Grant 8,196,291 - Pai June 12, 2	2012-06-12
Method for forming laminated multiple substrates Grant 8,028,403 - Pai , et al. October 4, 2	2011-10-04
Integrated Circuits Having Lead Contacts And Leadless Contact Pads Connected To A Surface Of A Printed Wiring Board, And Methods For Connecting The Same App 20110157855 - Pai; Deepak K.	2011-06-30
Apparatus and methods of attaching hybrid vlsi chips to printed wiring boards App 20110101075 - Pai; Deepak K.	2011-05-05
Method and apparatus to change solder pad size using a differential pad plating Grant 7,892,441 - Pai February 22, 2	2011-02-22
Method and apparatus for compliantly connecting stack of high-density electronic modules in harsh environments Grant 7,818,879 - Pai October 26, 2	2010-10-26
System and method of using a compliant lead interposer App 20100175248 - Pai; Deepak K.	2010-07-15
System and method of using a compliant lead interposer Grant 7,684,205 - Pai March 23, 2	2010-03-23
Apparatus and method for a segmented squeegee for stenciling Grant 7,614,341 - Pai , et al. November 10, 2	2009-11-10
Apparatus and methods of attaching hybrid vlsi chips to printed wiring boards App 20090250506 - Pai; Deepak K.	2009-10-08
Technique for laminating multiple substrates App 20090151158 - Pai; Deepak K. ; et al.	2009-06-18
Technique for laminating multiple substrates Grant 7,490,402 - Pai , et al. February 17, 2	2009-02-17
Method and apparatus to change solder pad size using a differential pad plating App 20080296253 - Pai; Deepak K.	2008-12-04
System and method for manufacturing C-shaped leads App 20080106877 - Pai; Deepak K.	2008-05-08
Technique for laminating multiple substrates App 20080066304 - Pai; Deepak K. ; et al.	2008-03-20
Laminated multiple substrates Grant 7,282,787 - Pai , et al. October 16, 2	2007-10-16
Optical fiber cable to inject or extract light App 20070193772 - Pai; Deepak K.	2007-08-23
Laminated multilayer package Grant 6,856,008 - Pai , et al. February 15, 2	2005-02-15
Method and apparatus to compliantly interconnect commercial-off-the-shelf chip scale packages and printed wiring boards Grant 6,830,177 - Pai December 14, 2	2004-12-14
Technique for laminating multiple substrates App 20040246688 - Pai, Deepak K. ; et al.	2004-12-09
Process for manufacturing laminated high layer count printed circuit boards Grant 6,742,247 - Pai , et al. June 1, 2	2004-06-01
Laminated multilayer package App 20040032028 - Pai, Deepak K. ; et al.	2004-02-19
Lamination of high-layer-count substrates App 20030174484 - Pai, Deepak K. ; et al.	2003-09-18
Method and apparatus to compliantly interconnect commercial-off-the-shelf chip scale packages and printed wiring boards App 20030049952 - Pai, Deepak K.	2003-03-13
Method and apparatus to compliantly interconnect area grid arrays and printed wiring boards Grant 6,493,238 - Pai December 10, 2	2002-12-10
Laminated multilayer substrates Grant 5,986,339 - Pai , et al. November 16, 1	1999-11-16
Method of performing an operation on an integrated circuit Grant 5,977,784 - Pai November 2, 1	1999-11-02
Laminated multilayer substrates Grant 5,786,238 - Pai , et al. July 28, 1	1998-07-28
Mask alignment mark system Grant 5,407,763 - Pai April 18, 1	1995-04-18
Plated compliant lead Grant 5,317,479 - Pai , et al. May 31, 1	1994-05-31
Plated compliant lead Grant 5,294,039 - Pai , et al. March 15, 1	1994-03-15
Hermetically sealed circuit modules having conductive cap anchors Grant 5,280,413 - Pai January 18, 1	1994-01-18
Compliant S-leads for chip carriers Grant 4,827,611 - Pai , et al. May 9, 1	1989-05-09

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