| Patent | Date |
|---|
Semiconductor wafer and die that include an integrated circuit and two or more different MEMS-based semiconductor devices
Grant 8,288,834 - Padmanabhan , et al. October 16, 2 | 2012-10-16 |
Method of forming a metal interconnect with capacitive structures that adjust the capacitance of the interconnect
Grant 7,790,602 - Yegnashankaran , et al. September 7, 2 | 2010-09-07 |
MEMS semiconductor sensor device
Grant 7,633,131 - Padmanabhan , et al. December 15, 2 | 2009-12-15 |
Method of forming a MOS transistor with a litho-less gate
Grant 7,482,228 - Padmanabhan , et al. January 27, 2 | 2009-01-27 |
Sensor configuration for a capsule endoscope
Grant 7,399,274 - Halla , et al. July 15, 2 | 2008-07-15 |
Method of forming a semiconductor die with heat and electrical pipes
Grant 7,338,840 - Padmanabhan , et al. March 4, 2 | 2008-03-04 |
Method of selectively forming MEMS-based semiconductor devices at the end of a common fabrication process
Grant 7,329,555 - Padmanabhan , et al. February 12, 2 | 2008-02-12 |
Single-crystal silicon semiconductor structure
Grant 7,230,301 - Padmanabhan , et al. June 12, 2 | 2007-06-12 |
Semiconductor sensor device using MEMS technology
Grant 7,192,819 - Padmanabhan , et al. March 20, 2 | 2007-03-20 |
Method of forming a hermetic seal for silicon die with metal feed through structure
Grant 7,109,571 - Padmanabhan , et al. September 19, 2 | 2006-09-19 |
Semiconductor die with heat and electrical pipes
Grant 7,075,133 - Padmanabhan , et al. July 11, 2 | 2006-07-11 |
Method of dicing a semiconductor wafer that substantially reduces the width of the saw street
Grant 7,052,977 - Yegnashankaran , et al. May 30, 2 | 2006-05-30 |
Method and system for dynamically adjusting field of view in a capsule endoscope
Grant 7,044,908 - Montalbo , et al. May 16, 2 | 2006-05-16 |
Multilevel metal interconnect and method of forming the interconnect with capacitive structures that adjust the capacitance of the interconnect
Grant 7,042,092 - Yegnashankaran , et al. May 9, 2 | 2006-05-09 |
Method of forming a vertical MOS transistor
Grant 6,949,421 - Padmanabhan , et al. September 27, 2 | 2005-09-27 |
Method of forming the integrated circuit having a die with high Q inductors and capacitors attached to a die with a circuit as a flip chip
Grant 6,946,321 - Yegnashankaran , et al. September 20, 2 | 2005-09-20 |
High Q inductor in multi-level interconnect
Grant 6,833,781 - Padmanabhan , et al. December 21, 2 | 2004-12-21 |
Integrated circuit and method of forming the integrated circuit having a die with high Q inductors and capacitors attached to a die with a circuit as a flip chip
Grant 6,781,239 - Yegnashankaran , et al. August 24, 2 | 2004-08-24 |
Vertical MOS transistor
Grant 6,777,288 - Padmanabhan , et al. August 17, 2 | 2004-08-17 |
Hermetic seal for silicon die with metal feed through structure
Grant 6,746,956 - Padmanabhan , et al. June 8, 2 | 2004-06-08 |
Radiation hardened MOS transistor
Grant 6,730,969 - Padmanabhan , et al. May 4, 2 | 2004-05-04 |
Deep submicron MOS transistor with increased threshold voltage
Grant 6,723,593 - Padmanabhan , et al. April 20, 2 | 2004-04-20 |
Silicon die with metal feed through structure
Grant 6,677,235 - Yegnashankaran , et al. January 13, 2 | 2004-01-13 |
Programmable polysilicon gate array base cell architecture
Grant 5,917,207 - Colwell , et al. June 29, 1 | 1999-06-29 |
Semiconductor chip package with interconnect layers and routing and testing methods
Grant 5,777,383 - Stager , et al. July 7, 1 | 1998-07-07 |
Method of forming a high electromigration resistant metallization system
Grant 5,776,831 - Padmanabhan , et al. July 7, 1 | 1998-07-07 |
Array of solder pads on an integrated circuit
Grant 5,731,223 - Padmanabhan March 24, 1 | 1998-03-24 |
Method of fabricating a programmable polysilicon gate array base cell structure
Grant 5,691,218 - Colwell , et al. November 25, 1 | 1997-11-25 |
Barrier metal technology for tungsten plug interconnection
Grant 5,600,182 - Schinella , et al. February 4, 1 | 1997-02-04 |
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