Padalia; Ketan

Patent Applications and Registrations

Patent applications and USPTO patent grants for Padalia; Ketan.The latest application filed is for "method and apparatus for performing fast incremental physical design optimization".

Company Profile

2.27.7

Padalia; Ketan - Richmond Hill CA
Padalia; Ketan - Thronhill CA
Padalia; Ketan - Thornhill CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and apparatus for performing fast incremental physical design optimization Grant 11,093,672 - Khan , et al. August 17, 2	2021-08-17
Method And Apparatus For Performing Fast Incremental Physical Design Optimization App 20200257839 - A1	2020-08-13
Method and apparatus for performing fast incremental physical design optimization Grant 10,635,772 - Khan , et al.	2020-04-28
Method and apparatus for performing efficient incremental compilation Grant 10,073,941 - Padalia , et al. September 11, 2	2018-09-11
Structures For Lut-based Arithmetic In Plds App 20170322775 - Padalia; Ketan ; et al.	2017-11-09
Structures for LUT-based arithmetic in PLDs Grant 9,658,830 - Padalia , et al. May 23, 2	2017-05-23
Apparatus and associated methods for parallelizing clustering and placement Grant 9,594,859 - Padalia , et al. March 14, 2	2017-03-14
Method and apparatus for performing fast incremental physical design optimization Grant 9,569,574 - Khan , et al. February 14, 2	2017-02-14
Method and apparatus for performing efficient incremental compilation Grant 8,856,713 - Padalia , et al. October 7, 2	2014-10-07
Structures for LUT-based arithmetic in PLDs Grant 8,788,550 - Padalia , et al. July 22, 2	2014-07-22
Method and apparatus for performing efficient incremental compilation Grant 8,539,418 - Padalia , et al. September 17, 2	2013-09-17
Method and apparatus for performing automated timing closure analysis for systems implemented on target devices Grant 8,504,970 - Malhotra , et al. August 6, 2	2013-08-06
Systems and methods for optimizing placement and routing Grant 8,499,273 - Bozman , et al. July 30, 2	2013-07-30
Method and apparatus for performing efficient incremental compilation Grant 8,281,274 - Padalia , et al. October 2, 2	2012-10-02
Techniques for grouping circuit elements into logic blocks Grant 7,707,532 - Padalia , et al. April 27, 2	2010-04-27
Apparatus and Methods for Parallelizing Integrated Circuit Computer-Aided Design Software App 20100070979 - Ludwin; Adrian ; et al.	2010-03-18
Apparatus and methods for congestion estimation and optimization for computer-aided design software Grant 7,681,165 - Peters , et al. March 16, 2	2010-03-16
Structures for LUT-based arithmetic in PLDs Grant 7,558,812 - Padalia , et al. July 7, 2	2009-07-07
Methods of packing user logical RAM into dedicated RAM blocks and dual-use logic/RAM blocks Grant 7,493,585 - Ahmed , et al. February 17, 2	2009-02-17
Methods for designing integrated circuits Grant 7,441,208 - Padalia , et al. October 21, 2	2008-10-21
Automatic adjustment of optimization effort in configuring programmable devices Grant 7,415,682 - Padalia , et al. August 19, 2	2008-08-19
Method for mapping logic design memory into physical memory devices of a programmable logic device Grant 7,370,291 - Fung , et al. May 6, 2	2008-05-06
Apparatus and Methods for Congestion Estimation and Optimization for Computer-Aided Design Software App 20080059931 - Peters; Jason ; et al.	2008-03-06
Techniques for grouping circuit elements into logic blocks Grant 7,275,228 - Padalia , et al. September 25, 2	2007-09-25
Adder circuitry for a programmable logic device Grant 7,268,584 - Cashman , et al. September 11, 2	2007-09-11
Apparatus and methods for parallelizing integrated circuit computer-aided design software App 20070192766 - Padalia; Ketan ; et al.	2007-08-16
Automatic adjustment of optimization effort in configuring programmable devices App 20060225021 - Padalia; Ketan ; et al.	2006-10-05
Method for mapping logic design memory into physical memory devices of a programmable logic device App 20050204325 - Fung, Ryan ; et al.	2005-09-15
Method for mapping logic design memory into physical memory device of a programmable logic device Grant 6,871,328 - Fung , et al. March 22, 2	2005-03-22

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