PACT XPP TECHNOLOGIES AG

Patent Applications and Registrations

Patent applications and USPTO patent grants for PACT XPP TECHNOLOGIES AG.The latest application filed is for "array processor having a segmented bus system".

Company Profile

0.75.66

PACT XPP TECHNOLOGIES AG - Munich DE
PACT XPP TECHNOLOGIES AG -
PACT XPP TECHNOLOGIES AG - Munchen DE
PACT XPP Technologies AG - Muthmannstrasse 1 Munchen DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Trademarks

Patent Activity

Patent	Date
Array Processor Having a Segmented Bus System App 20180300278 - VORBACH; Martin ; et al.	2018-10-18
Multi-processor With Selectively Interconnected Memory Units App 20180067896 - Vorbach; Martin	2018-03-08
Multi-processor with selectively interconnected memory units Grant 9,817,790 - Vorbach November 14, 2	2017-11-14
Method For Providing Subapplications To An Array Of Alus App 20170286364 - Vorbach; Martin ; et al.	2017-10-05
Methods and devices for treating and processing data App 20170192481 - Vorbach; Martin ; et al.	2017-07-06
Configurable logic integrated circuit having a multidimensional structure of configurable elements Grant 9,690,747 - Vorbach , et al. June 27, 2	2017-06-27
Array processor having a segmented bus system Grant 9,626,325 - Vorbach , et al. April 18, 2	2017-04-18
Multiprocessor having runtime adjustable clock and clock dependent power supply Grant 9,552,047 - Vorbach , et al. January 24, 2	2017-01-24
Method of Transferring Data between External Devices and an Array Processor App 20160357555 - Vorbach; Martin ; et al.	2016-12-08
Chip including memory element storing higher level memory data on a page by page basis Grant 9,436,631 - Vorbach September 6, 2	2016-09-06
Methods and systems for transferring data between a processing device and external devices Grant 9,411,532 - Vorbach , et al. August 9, 2	2016-08-09
Multi-processor with selectively interconnected memory units App 20160170925 - Vorbach; Martin	2016-06-16
Array Processor Having a Segmented Bus System App 20160154758 - VORBACH; Martin ; et al.	2016-06-02
Processor Having a Programmable Function Unit App 20160141050 - Vorbach; Martin	2016-05-19
Multi-processor with selectively interconnected memory units Grant 9,274,984 - Vorbach March 1, 2	2016-03-01
Integrated data processing core and array data processor and method for processing algorithms App 20160055120 - Vorbach; Martin ; et al.	2016-02-25
Data processor chip with flexible bus system Grant 9,256,575 - Vorbach , et al. February 9, 2	2016-02-09
Multi-processor bus and cache interconnection system Grant 9,250,908 - Vorbach , et al. February 2, 2	2016-02-02
Stacked-die multi-processor Grant 9,240,220 - Vorbach January 19, 2	2016-01-19
Stacked-die Multi-processor App 20150371683 - Vorbach; Martin	2015-12-24
Data processing system having integrated pipelined array data processor Grant 9,170,812 - Vorbach , et al. October 27, 2	2015-10-27
Data processor chip with flexible bus system App 20150261722 - VORBACH; Martin ; et al.	2015-09-17
Methods and Systems for Transferring Data between a Processing Device and External Devices App 20150261474 - Vorbach; Martin ; et al.	2015-09-17
Multiprocessor having associated RAM units Grant 9,092,595 - Vorbach July 28, 2	2015-07-28
Methods and devices for treating and processing data Grant 9,075,605 - Vorbach , et al. July 7, 2	2015-07-07
Logical cell array and bus system Grant 9,047,440 - Vorbach , et al. June 2, 2	2015-06-02
Processor arrangement on a chip including data processing, memory, and interface elements Grant 9,037,807 - Vorbach May 19, 2	2015-05-19
Data Processing System Having Integrated Pipelined Array Data Processor App 20150106596 - Vorbach; Martin ; et al.	2015-04-16
Configurable Logic Integrated Circuit Having A Multidimensional Structure Of Configurable Elements App 20150100756 - Vorbach; Martin ; et al.	2015-04-09
Multiprocessor Having Associated RAM Units App 20150082003 - Vorbach; Martin	2015-03-19
Multiprocessor Having Segmented Cache Memory App 20150074352 - Vorbach; Martin	2015-03-12
Parallel Processing Array of Arithmetic Unit having a Barrier Instruction App 20150033000 - Vorbach; Martin ; et al.	2015-01-29
Method of Processing Data with an Array of Data Processors According to Application ID App 20150026431 - Vorbach; Martin ; et al.	2015-01-22
Multi-core processor having disabled cores Grant 8,914,690 - Vorbach , et al. December 16, 2	2014-12-16
Data processing method and device Grant 8,914,590 - Vorbach , et al. December 16, 2	2014-12-16
Coarse-Grained Data Processor Having Both Global and Direct Interconnects App 20140359255 - Vorbach; Martin ; et al.	2014-12-04
Logical cell array and bus system App 20140359254 - Vorbach; Martin ; et al.	2014-12-04
Multi-processor with selectively interconnected memory units App 20140351482 - Vorbach; Martin	2014-11-27
Reconfigurable elements Grant 8,890,215 - Vorbach November 18, 2	2014-11-18
Configurable Logic Integrated Circuit Having A Multidimensional Structure Of Configurable Elements App 20140337601 - Vorbach; Martin ; et al.	2014-11-13
Method for manufacturing a chip from a system definition App 20140331194 - Vorbach; Martin ; et al.	2014-11-06
Pipeline Configuration Protocol And Configuration Unit Communication App 20140325175 - Vorbach; Martin ; et al.	2014-10-30
Method of self-synchronization of configurable elements of a programmable module Grant RE45,223 - Vorbach , et al. October 28, 2	2014-10-28
Method for the translation of programs for reconfigurable architectures Grant 8,869,121 - Vorbach , et al. October 21, 2	2014-10-21
Multi-processor bus and cache interconnection system App 20140310466 - Vorbach; Martin ; et al.	2014-10-16
Multi-core processor having disabled cores App 20140304449 - Vorbach; Martin ; et al.	2014-10-09
Chip Including Memory Element Storing Higher Level Memory Data On A Page By Page Basis App 20140297914 - Vorbach; Martin	2014-10-02
Method For Processing Data App 20140297948 - VORBACH; Martin ; et al.	2014-10-02
Method of self-synchronization of configurable elements of a programmable module Grant RE45,109 - Vorbach , et al. September 2, 2	2014-09-02
Reconfigurable Elements App 20140244973 - Vorbach; Martin	2014-08-28
Data processor having disabled cores Grant 8,819,505 - Vorbach , et al. August 26, 2	2014-08-26
Data processing device and method Grant 8,812,820 - Vorbach , et al. August 19, 2	2014-08-19
Reconfigurable sequencer structure Grant 8,803,552 - Vorbach August 12, 2	2014-08-12
Multiprocessor Having Runtime Adjustable Clock and Clock Dependent Power Supply App 20140208143 - VORBACH; Martin ; et al.	2014-07-24
Method And Device For Data Processing App 20140143509 - Vorbach; Martin	2014-05-22
Configurable logic integrated circuit having a multidimensional structure of configurable elements Grant 8,726,250 - Vorbach , et al. May 13, 2	2014-05-13
Reconfigurable elements Grant 8,686,475 - Vorbach April 1, 2	2014-04-01
Method For Debugging Reconfigurable Architectures App 20130339797 - Vorbach; Martin	2013-12-19
Method for debugging reconfigurable architectures Grant 8,407,525 - Vorbach March 26, 2	2013-03-26
Methods And Devices For Treating And Processing Data App 20130042137 - VORBACH; Martin ; et al.	2013-02-14
Reconfigurable Sequencer Structure App 20130024657 - VORBACH; Martin	2013-01-24
Method and device for processing data Grant 7,657,861 - Vorbach , et al. February 2, 2	2010-02-02
Method for processing data Grant 7,657,877 - Vorbach , et al. February 2, 2	2010-02-02
I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures Grant 7,650,448 - Vorbach , et al. January 19, 2	2010-01-19
Reconfigurable sequencer structure Grant 7,602,214 - Vorbach October 13, 2	2009-10-13
Logic cell array and bus system Grant 7,595,659 - Vorbach , et al. September 29, 2	2009-09-29
Method and system for alternating between programs for execution by cells of an integrated circuit Grant 7,584,390 - Vorbach , et al. September 1, 2	2009-09-01
Methods and devices for treating and/or processing data Grant 7,581,076 - Vorbach August 25, 2	2009-08-25
Method And Device For Treating And Processing Data App 20090210653 - Vorbach; Martin ; et al.	2009-08-20
Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization Grant 7,577,822 - Vorbach August 18, 2	2009-08-18
Runtime configurable arithmetic and logic cell Grant 7,565,525 - Vorbach , et al. July 21, 2	2009-07-21
Method for debugging reconfigurable architectures Grant 7,480,825 - Vorbach January 20, 2	2009-01-20
Methods and devices for treating and processing data Grant 7,444,531 - Vorbach , et al. October 28, 2	2008-10-28
Router Grant 7,434,191 - Vorbach , et al. October 7, 2	2008-10-07
Reconfigurable sequencer structure Grant 7,394,284 - Vorbach July 1, 2	2008-07-01
I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures Grant 7,337,249 - Vorbach , et al. February 26, 2	2008-02-26
Method and Device for Treating and Processing Data App 20070299993 - Vorbach; Martin ; et al.	2007-12-27
Method for debugging reconfigurable architectures Grant 7,266,725 - Vorbach , et al. September 4, 2	2007-09-04
I/O and memory bus system for DFPs and units with two-or multi-dimensional programmable cell architectures Grant 7,243,175 - Vorbach , et al. July 10, 2	2007-07-10
Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells Grant 7,237,087 - Vorbach , et al. June 26, 2	2007-06-26
Method for translating programs for reconfigurable architectures Grant 7,210,129 - May , et al. April 24, 2	2007-04-24
Run-time reconfiguration method for programmable units Grant 7,174,443 - Vorbach , et al. February 6, 2	2007-02-06
Method of self-synchronization of configurable elements of a programmable module Grant 7,036,036 - Vorbach , et al. April 25, 2	2006-04-25
Process for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three- dimensional programmable cell architectures (FPGAS, DPGAS, and the like) Grant 7,028,107 - Vorbach , et al. April 11, 2	2006-04-11
Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity Grant 7,010,667 - Vorbach , et al. March 7, 2	2006-03-07
Pipeline configuration unit protocols and communication Grant 7,003,660 - Vorbach , et al. February 21, 2	2006-02-21
Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.) Grant 6,990,555 - Vorbach , et al. January 24, 2	2006-01-24
Method of self-synchronization of configurable elements of a programmable unit Grant 6,968,452 - Vorbach , et al. November 22, 2	2005-11-22
Data processing system Grant 6,859,869 - Vorbach February 22, 2	2005-02-22
Runtime configurable arithmetic and logic cell Grant 6,728,871 - Vorbach , et al. April 27, 2	2004-04-27
I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures Grant 6,721,830 - Vorbach , et al. April 13, 2	2004-04-13
Method of repairing integrated circuits Grant 6,697,979 - Vorbach , et al. February 24, 2	2004-02-24
Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.) Grant 6,687,788 - Vorbach , et al. February 3, 2	2004-02-03
Method for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.) Grant 6,571,381 - Vorbach , et al. May 27, 2	2003-05-27

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