Pack; Robert C.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Pack; Robert C..The latest application filed is for "method and system for dimensional uniformity using charged particle beam lithography".

Company Profile

0.20.15

Pack; Robert C. - Morgan Hill CA
Pack; Robert C. - Foster City CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and system for dimensional uniformity using charged particle beam lithography Grant 10,431,422 - Fujimura , et al. O	2019-10-01
Method, system and program product for identifying anomalies in integrated circuit design layouts Grant 10,055,535 - Pathak , et al. August 21, 2	2018-08-21
Method And System For Dimensional Uniformity Using Charged Particle Beam Lithography App 20180108513 - Fujimura; Akira ; et al.	2018-04-19
Method, System And Program Product For Identifying Anomalies In Integrated Circuit Design Layouts App 20180089357 - PATHAK; Piyush ; et al.	2018-03-29
Method and system for dimensional uniformity using charged particle beam lithography Grant 9,859,100 - Fujimura , et al. January 2, 2	2018-01-02
Method And System For Dimensional Uniformity Using Charged Particle Beam Lithography App 20160260581 - Fujimura; Akira ; et al.	2016-09-08
Method and system for dimensional uniformity using charged particle beam lithography Grant 9,343,267 - Fujimura , et al. May 17, 2	2016-05-17
Method and system for critical dimension uniformity using charged particle beam lithography Grant 9,038,003 - Pearman , et al. May 19, 2	2015-05-19
Method and system for dimensional uniformity using charged particle beam lithography Grant 8,959,463 - Fujimura , et al. February 17, 2	2015-02-17
Method And System For Dimensional Uniformity Using Charged Particle Beam Lithography App 20140359542 - Fujimura; Akira ; et al.	2014-12-04
Method and system for forming high precision patterns using charged particle beam lithography Grant 8,745,549 - Fujimura , et al. June 3, 2	2014-06-03
Method And System For Dimensional Uniformity Using Charged Particle Beam Lithography App 20140129996 - Fujimura; Akira ; et al.	2014-05-08
Method And System For Dimensional Uniformity Using Charged Particle Beam Lithography App 20140129997 - Fujimura; Akira ; et al.	2014-05-08
Method And System For Critical Dimension Uniformity Using Charged Particle Beam Lithography App 20130283216 - Pearman; Ryan ; et al.	2013-10-24
Method And System For Forming High Precision Patterns Using Charged Particle Beam Lithography App 20130205264 - Fujimura; Akira ; et al.	2013-08-08
Modeling and simulating the impact of imperfectly patterned via arrays on integrated circuits Grant 8,468,482 - Pack , et al. June 18, 2	2013-06-18
Hierarchical variation analysis of integrated circuits Grant 8,453,102 - Pack , et al. May 28, 2	2013-05-28
Method and system for context-specific mask inspection Grant 8,407,627 - Pack , et al. March 26, 2	2013-03-26
Method and system for context-specific mask writing Grant 7,784,016 - Pack , et al. August 24, 2	2010-08-24
Method and system for context-specific mask writing Grant 7,302,672 - Pack , et al. November 27, 2	2007-11-27
Method and System for Context-Specific Mask Writing App 20070266364 - Pack; Robert C. ; et al.	2007-11-15
Method and System for Context-Specific Mask Inspection App 20070233419 - Pack; Robert C. ; et al.	2007-10-04
Method and system for context-specific mask writing Grant 7,249,342 - Pack , et al. July 24, 2	2007-07-24
Method and system for context-specific mask inspection Grant 7,231,628 - Pack , et al. June 12, 2	2007-06-12
Method for creating patterns for producing integrated circuits Grant 7,024,638 - Scheffer , et al. April 4, 2	2006-04-04
Method and system for context-specific mask writing App 20050216877 - Pack, Robert C. ; et al.	2005-09-29
Method for creating patterns for producing integrated circuits App 20050015739 - Scheffer, Louis K. ; et al.	2005-01-20
Method and system for context-specific mask inspection App 20040133369 - Pack, Robert C. ; et al.	2004-07-08
Method and system for context-specific mask writing App 20040107412 - Pack, Robert C. ; et al.	2004-06-03
Integrated scheme for predicting yield of semiconductor (MOS) devices from designed layout Grant 6,562,638 - Balasinski , et al. May 13, 2	2003-05-13

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.