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Patent applications and USPTO patent grants for Pacheco Rotondaro; Antonio Luis.The latest application filed is for "semiconductor device with gate-undercutting recessed region".
Patent | Date |
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Semiconductor device with gate-undercutting recessed region Grant 8,329,589 - Pacheco Rotondaro , et al. December 11, 2 | 2012-12-11 |
Semiconductor device with gate-undercutting recessed region Grant 8,288,805 - Pacheco Rotondaro , et al. October 16, 2 | 2012-10-16 |
Semiconductor Device With Gate-undercutting Recessed Region App 20110316089 - PACHECO ROTONDARO; Antonio Luis ;   et al. | 2011-12-29 |
Semiconductor device with gate-undercutting recessed region Grant 8,049,254 - Pacheco Rotondaro , et al. November 1, 2 | 2011-11-01 |
Semiconductor Device With Gate-undercutting Recessed Region App 20090174005 - Pacheco Rotondaro; Antonio Luis ;   et al. | 2009-07-09 |
Work function control of metals Grant 7,291,527 - Chambers , et al. November 6, 2 | 2007-11-06 |
Method to Reduce Transistor Gate to Source/Drain Overlap Capacitance by Incorporation of Carbon App 20070166906 - Mansoori; Majid Movahed ;   et al. | 2007-07-19 |
Methods for reduced circuit area and improved gate length control App 20060113604 - Tigelaar; Howard Lee ;   et al. | 2006-06-01 |
Systems and methods for low leakage strained-channel transistor Grant 7,026,232 - Koontz , et al. April 11, 2 | 2006-04-11 |
Method to selectively strain NMOS devices using a cap poly layer App 20060073650 - Sridhar; Seetharaman ;   et al. | 2006-04-06 |
High-K gate dielectric defect gettering using dopants Grant 7,015,088 - Colombo , et al. March 21, 2 | 2006-03-21 |
Methods for forming interfacial layer for deposition of high-k dielectrics App 20040126944 - Pacheco Rotondaro, Antonio Luis ;   et al. | 2004-07-01 |
Noval chemistry and method for the selective removal of high-k dielectrics App 20030109106 - Pacheco Rotondaro, Antonio Luis ;   et al. | 2003-06-12 |
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