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Restartable cache write-back and invalidation
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Restricting Usage Of Encryption Keys By Untrusted Software
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Apparatus And Method To Identify The Source Of An Interrupt
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System, apparatus and method for page granular,software controlled multiple key memory encryption
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Restricting usage of encryption keys by untrusted software
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Multi-key Cryptographic Memory Protection
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Executing Code In Protected Memory Containers By Trust Domains
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Apparatus and method to identify the source of an interrupt
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Branch prediction unit in service of short microcode flows
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Restartable Cache Write-back And Invalidation
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Branch Prediction Unit In Service Of Short Microcode Flows
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Avoiding asynchronous enclave exits based on requests to invalidate translation lookaside buffer entries
Grant 10,867,092 - Caspi , et al. December 15, 2 | 2020-12-15 |
Restartable cache write-back and invalidation
Grant 10,838,722 - Gerzon , et al. November 17, 2 | 2020-11-17 |
System, Apparatus And Method For Page Granular,Software Controlled Multiple Key Memory Encryption
App 20200226074 - Durham; David M. ; et al. | 2020-07-16 |
Restartable Cache Write-back And Invalidation
App 20200201638 - GERZON; Gideon ; et al. | 2020-06-25 |
Co-existence Of Trust Domain Architecture With Multi-key Total Memory Encryption Technology In Servers
App 20200201786 - OUZIEL; Ido ; et al. | 2020-06-25 |
Restricting Usage Of Encryption Keys By Untrusted Software
App 20200204356 - OUZIEL; Ido ; et al. | 2020-06-25 |
System, apparatus and method for page granular, software controlled multiple key memory encryption
Grant 10,657,071 - Durham , et al. | 2020-05-19 |
Multicore system for fusing instructions queued during a dynamically adjustable time window
Grant 10,649,783 - Ouziel , et al. | 2020-05-12 |
System, Apparatus And Method For Page Granular,Software Controlled Multiple Key Memory Encryption
App 20190095350 - Durham; David M. ; et al. | 2019-03-28 |
Providing Isolation In Virtualized Systems Using Trust Domains
App 20190087575 - Sahita; Ravi L. ; et al. | 2019-03-21 |
Method and apparatus for supporting quasi-posted loads
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Hardware mechanism for performing atomic actions on remote processors
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Avoiding Asynchronous Enclave Exits Based On Requests To Invalidate Translation Lookaside Buffer Entries
App 20190042671 - Caspi; Dror ; et al. | 2019-02-07 |
Multi-key Cryptographic Memory Protection
App 20190004973 - Chhabra; Siddhartha ; et al. | 2019-01-03 |
Method And Apparatus For Supporting Quasi-posted Loads
App 20180181393 - Ouziel; Ido ; et al. | 2018-06-28 |
Execution profiling mechanism
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Validating virtual address translation by virtual machine monitor utilizing address validation structure to validate tentative guest physical address and aborting based on flag in extended page table requiring an expected guest physical address in the address validation structure
Grant 9,792,222 - Sahita , et al. October 17, 2 | 2017-10-17 |
System and method for fusing instructions queued during a time window defined by a delay counter
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Hardware Mechanism for Performing Atomic Actions on Remote Processors
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Efficient Instruction Fusion By Fusing Instructions That Fall Within A Counter-tracked Amount Of Cycles Apart
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Efficient Instruction Fusion By Fusing Instructions That Fall Within A Counter-tracked Amount Of Cycles Apart
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Efficient Instruction Fusion By Fusing Instructions That Fall Within A Counter-tracked Amount Of Cycles Apart
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Execution Profiling Mechanism
App 20160180079 - Sahita; Ravi L. ; et al. | 2016-06-23 |
Method and apparatus for fine grain memory protection
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Validating Virtual Address Translation
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Method And Apparatus For Fine Grain Memory Protection
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Method and apparatus for inclusion of TLB entries in a micro-op cache of a processor
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Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor
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Efficient method and apparatus for employing a micro-op cache in a processor
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Representing a plurality of instructions with a fewer number of micro-operations
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Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor
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Method And Apparatus For Inclusion Of Tlb Entries In A Micro-op Cache Of A Processor
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Technique for promoting efficient instruction fusion
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Efficient Method And Apparatus For Employing A Micro-op Cache In A Processor
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