| Patent | Date |
|---|
Method of designing semiconductor device
Grant 11,449,656 - Wang , et al. September 20, 2 | 2022-09-20 |
Integrated Circuit And Method Of Forming Same And A System
App 20220198122 - CHEN; Sheng-Hsiung ; et al. | 2022-06-23 |
Multi-Row Standard Cell Design Method in Hybrid Row Height System
App 20220147687 - Ou; Hung-Chih ; et al. | 2022-05-12 |
Integrated circuit and method of forming same and a system
Grant 11,275,886 - Chen , et al. March 15, 2 | 2022-03-15 |
Multi-row standard cell design method in hybrid row height system
Grant 11,263,378 - Ou , et al. March 1, 2 | 2022-03-01 |
Integrated Circuit And Method Of Forming Same And A System
App 20210256193 - CHEN; Sheng-Hsiung ; et al. | 2021-08-19 |
Method and system for improving propagation delay of conductive line
Grant 11,087,061 - Ou , et al. August 10, 2 | 2021-08-10 |
Multi-Row Standard Cell Design Method in Hybrid Row Height System
App 20210224455 - Ou; Hung-Chih ; et al. | 2021-07-22 |
Method And System For Improving Propagation Delay Of Conductive Line
App 20210209281 - OU; HUNG-CHIH ; et al. | 2021-07-08 |
Integrated circuit and method of forming same and a system
Grant 10,990,745 - Chen , et al. April 27, 2 | 2021-04-27 |
Method Of Regulating Integrated Circuit Timing And Power Consumption
App 20210056250 - Ou; Hung-Chih ; et al. | 2021-02-25 |
Method Of Designing Semiconductor Device
App 20210004517 - WANG; Shao-Huan ; et al. | 2021-01-07 |
Method of regulating integrated circuit timing and power consumption
Grant 10,831,978 - Ou , et al. November 10, 2 | 2020-11-10 |
Method of designing semiconductor device and system for implementing the method
Grant 10,817,643 - Wang , et al. October 27, 2 | 2020-10-27 |
Integrated Circuit And Method Of Forming Same And A System
App 20200097634 - CHEN; Sheng-Hsiung ; et al. | 2020-03-26 |
Method Of Regulating Integrated Circuit Timing And Power Consumption
App 20200004919 - OU; Hung-Chih ; et al. | 2020-01-02 |
Method Of Designing Semiconductor Device And System For Implementing The Method
App 20190266309 - WANG; Shao-Huan ; et al. | 2019-08-29 |
Method, system, and storage medium for engineering change order scheme in circuit design
Grant 10,360,342 - Ou , et al. | 2019-07-23 |
Layout for semiconductor device including via pillar structure
Grant 10,289,794 - Wang , et al. | 2019-05-14 |
Method, System, And Storage Medium For Engineering Change Order Scheme In Circuit Design
App 20190080037 - OU; HUNG-CHIH ; et al. | 2019-03-14 |
Method and system for partitioning circuit cells
Grant 10,157,251 - Ou , et al. Dec | 2018-12-18 |
Layout For Semiconductor Device Including Via Pillar Structure
App 20180165403 - WANG; Shao-Huan ; et al. | 2018-06-14 |
Method and circuit for via pillar optimization
Grant 9,977,857 - Ku , et al. May 22, 2 | 2018-05-22 |
Method And System For Partitioning Circuit Cells
App 20180137230 - Ou; Hung-Chih ; et al. | 2018-05-17 |
Method for analog circuit placement
Grant 9,830,416 - Wu , et al. November 28, 2 | 2017-11-28 |
Method For Analog Circuit Placement
App 20170206298 - Wu; I-Peng ; et al. | 2017-07-20 |
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