Osler; Peter J.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Osler; Peter J..The latest application filed is for "method and system for providing secondary power pins in integrated circuit design".
- Osler; Peter J. - Jericho VT US
| Patent | Date |
|---|---|
| Providing secondary power pins in integrated circuit design Grant 8,495,547 - Keinert , et al. July 23, 2 | 2013-07-23 |
| Method and System for Providing Secondary Power Pins in Integrated Circuit Design App 20110113398 - Keinert; Joachim ; et al. | 2011-05-12 |
| Variable detail automatic invocation of transistor level timing for application specific integrated circuit static timing analysis Grant 6,829,755 - Gutwin , et al. December 7, 2 | 2004-12-07 |
| Variable Detail Automatic Invocation Of Transistor Level Timing For Application Specific Integrated Circuit Static Timing Analysis App 20030037306 - Gutwin, Paul T. ; et al. | 2003-02-20 |
| Method of partitioning large transistor design to facilitate transistor level timing App 20030033583 - Gutwin, Paul T. ; et al. | 2003-02-13 |
| Incremental design tuning and decision mediator Grant 6,425,110 - Hathaway , et al. July 23, 2 | 2002-07-23 |
| Guess mechanism for virtual address translation Grant 5,099,415 - Osler , et al. March 24, 1 | 1992-03-24 |
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