Optimal Test Ltd.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Optimal Test Ltd..The latest application filed is for "datalog management in semiconductor testing".
- Optimal Test Ltd. - Nes-Zionna IL
- OPTIMAL TEST LTD. -
| Patent | Date |
|---|---|
| Methods for slow test time detection of an integrated circuit during parallel testing Grant 7,528,622 - Balog , et al. May 5, 2 | 2009-05-05 |
| Datalog Management In Semiconductor Testing App 20090013218 - ROUSSEAU; Eran ; et al. | 2009-01-08 |
| Augmenting semiconductor's devices quality and reliability App 20080114558 - Erez; Nir ; et al. | 2008-05-15 |
| System and methods for test time outlier detection and correction in integrated circuit testing App 20070132477 - Balog; Gil ; et al. | 2007-06-14 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.
| 