Oprescu; Florin

Patent Applications and Registrations

Patent applications and USPTO patent grants for Oprescu; Florin.The latest application filed is for "simultaneously-sampling single-ended and differential two-input analog-to-digital converter".

Company Profile

0.21.1

Oprescu; Florin - San Diego CA
Oprescu; Florin - Sunnyvale CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Simultaneously-sampling single-ended and differential two-input analog-to-digital converter Grant 8,576,104 - Steensgaard-Madsen , et al. November 5, 2	2013-11-05
Simultaneously-sampling Single-ended And Differential Two-input Analog-to-digital Converter App 20120326909 - STEENSGAARD-MADSEN; Jesper ; et al.	2012-12-27
Method and apparatus for supplying power to devices coupled to a bus Grant 5,842,027 - Oprescu , et al. November 24, 1	1998-11-24
Method and apparatus for transforming an arbitrary topology collection of nodes into an acyclic directed graph Grant 5,784,557 - Oprescu July 21, 1	1998-07-21
High-speed dominant mode bus for differential signals Grant 5,778,204 - Van Brunt , et al. July 7, 1	1998-07-07
Power management system for computer device interconnection bus Grant 5,752,046 - Oprescu , et al. May 12, 1	1998-05-12
CMOS differential twisted-pair driver Grant 5,694,060 - Brunt , et al. December 2, 1	1997-12-02
Methods and apparatus for bus access arbitration of nodes organized into acyclic directed graph by cyclic token passing and alternatively propagating request to root node and grant signal to the child node Grant 5,630,173 - Oprescu May 13, 1	1997-05-13
Delay line separator for data bus Grant 5,619,541 - Van Brunt , et al. April 8, 1	1997-04-08
Communication node with a first bus configuration for arbitration and a second bus configuration for data transfer Grant 5,579,486 - Oprescu , et al. November 26, 1	1996-11-26
Method and apparatus for a dynamic, multi-speed bus architecture in which an exchange of speed messages occurs independent of the data signal transfers Grant 5,559,967 - Oprescu , et al. September 24, 1	1996-09-24
Method and apparatus for a dynamic, multi-speed bus architecture having a scalable interface Grant 5,509,126 - Oprescu , et al. April 16, 1	1996-04-16
Bus interconnect circuit including port control logic for a multiple node communication network Grant 5,485,458 - Oprescu , et al. January 16, 1	1996-01-16
System for managing power consumption of devices coupled to a common bus Grant 5,483,656 - Oprescu , et al. January 9, 1	1996-01-09
Method and apparatus for implementing a common mode level shift in a bus transceiver incorporating a high speed binary data transfer mode with a ternary control transfer mode Grant 5,424,657 - Van Brunt , et al. June 13, 1	1995-06-13
Delay line separator for data bus Grant 5,412,697 - Van Brunt , et al. May 2, 1	1995-05-02
Adaptive data separator Grant 5,412,698 - Van Brunt , et al. May 2, 1	1995-05-02
Method and apparatus for unique address assignment, node self-identification and topology mapping for a directed acyclic graph Grant 5,394,556 - Oprescu February 28, 1	1995-02-28
Method and apparatus for transmitting NRZ data signals across an isolation barrier disposed in an interface between adjacent devices on a bus Grant 5,384,808 - Van Brunt , et al. January 24, 1	1995-01-24
Method and apparatus for a bus transceiver incorporating a high speed binary data transfer mode with a ternary control transfer mode having a full duplex, dominant logic transmission scheme Grant 5,384,769 - Oprescu , et al. * January 24, 1	1995-01-24
Method and apparatus for implementing a common mode level shift in a bus transceiver incorporating a high speed binary data transfer mode with a ternary control transfer mode Grant 5,325,355 - Oprescu , et al. June 28, 1	1994-06-28

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