Ooshima; Satoru

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ooshima; Satoru.The latest application filed is for "communication system and antenna apparatus".

Company Profile

0.7.8

Ooshima; Satoru - Tokyo JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Communication system using transmit/receive slot antennas for near field electromagnetic coupling of data therebetween Grant 8,121,544 - Shimizu , et al. February 21, 2	2012-02-21
Signal processing device Grant 7,956,660 - Ooshima , et al. June 7, 2	2011-06-07
Wireless communication apparatus, wireless network system, communication method and program Grant 7,801,574 - Ueda , et al. September 21, 2	2010-09-21
Phase error determination method and digital phase-locked loop system Grant 7,730,366 - Nakamura , et al. June 1, 2	2010-06-01
Communication System And Antenna Apparatus App 20090273418 - Shimizu; Tatsuo ; et al.	2009-11-05
Signal Processing Device App 20090243685 - OOSHIMA; Satoru ; et al.	2009-10-01
Phase error determination method and digital phase-locked loop system Grant 7,469,367 - Nakamura , et al. December 23, 2	2008-12-23
Digital PLL device Grant 7,342,986 - Nakamura , et al. March 11, 2	2008-03-11
Phase error determination method and digital phase-locked loop system Grant 7,315,968 - Nakamura , et al. January 1, 2	2008-01-01
Phase error determination method and digital phase-locked loop system App 20070094549 - Nakamura; Shinobu ; et al.	2007-04-26
Phase error determination method and digital phase-locked loop system App 20070088992 - Nakamura; Shinobu ; et al.	2007-04-19
Wireless communication apparatus, wireless network system, communication method and program App 20060270437 - Ueda; Satoshi ; et al.	2006-11-30
Wireless communication apparatus, communication system, communication method, and program App 20060193287 - Ooshima; Satoru ; et al.	2006-08-31
Phase error determination method and digital phase-locked loop system App 20050022076 - Nakamura, Shinobu ; et al.	2005-01-27
Digital PLL device App 20040264623 - Nakamura, Shinobu ; et al.	2004-12-30

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