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Onodera; Tadashi Patent Filings

Onodera; Tadashi

Patent Applications and Registrations

Patent applications and USPTO patent grants for Onodera; Tadashi.The latest application filed is for "semiconductor device testable on quality of multiple memory cells in parallel and testing method of the same".

Company Profile
0.6.5
  • Onodera; Tadashi - Tokyo JP
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Semiconductor device testable on quality of multiple memory cells in parallel and testing method of the same
Grant 7,978,543 - Inaba , et al. July 12, 2
2011-07-12
Semiconductor Device Testable On Quality Of Multiple Memory Cells In Parallel And Testing Method Of The Same
App 20090316495 - INABA; Hideo ;   et al.
2009-12-24
Self-refresh timer circuit and method of adjusting self-refresh timer period
Grant 7,515,496 - Matsui , et al. April 7, 2
2009-04-07
Delay circuit and semiconductor device
Grant 7,432,753 - Onodera October 7, 2
2008-10-07
Self-refresh timer circuit and method of adjusting self-refresh timer period
App 20080074940 - Matsui; Yoshinori ;   et al.
2008-03-27
Delay circuit and semiconductor device
App 20080048749 - ONODERA; Tadashi
2008-02-28
Self-refresh timer circuit and method of adjusting self-refresh timer period
Grant 7,307,909 - Matsui , et al. December 11, 2
2007-12-11
Delay circuit and semiconductor device
Grant 7,292,086 - Onodera November 6, 2
2007-11-06
Self-refresh timer circuit and method of adjusting self-refresh timer period
App 20060145667 - Matsui; Yoshinori ;   et al.
2006-07-06
Delay circuit and semiconductor device
App 20060139079 - Onodera; Tadashi
2006-06-29
Semiconductor memory device
Grant 6,335,889 - Onodera January 1, 2
2002-01-01

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