Ong; Shiang Yang

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ong; Shiang Yang.The latest application filed is for "contact structures to deep trench isolation structures and method of nanufacturing the same".

Company Profile

6.25.29

Ong; Shiang Yang - Singapore SG
Ong; Shiang Yang - Dresden DE
Ong; Shiang Yang - US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
High voltage Schottky diode and manufacturing method thereof Grant 10,529,819 - Mun , et al. J	2020-01-07
Contact Structures To Deep Trench Isolation Structures And Method Of Nanufacturing The Same App 20200006111 - DONG; Ke ; et al.	2020-01-02
Low on resistance high voltage metal oxide semiconductor transistor Grant 10,510,831 - Mun , et al. Dec	2019-12-17
Contact structures to deep trench isolation structures and method of nanufacturing the same Grant 10,504,768 - Dong , et al. Dec	2019-12-10
Low On Resistance High Voltage Metal Oxide Semiconductor Transistor App 20190259829 - MUN; Namchil ; et al.	2019-08-22
High Voltage Schottky Diode And Manufacturing Method Thereof App 20190140071 - MUN; Namchil ; et al.	2019-05-09
Integrated circuits with deep trench isolations and methods for producing the same Grant 9,831,304 - Yap , et al. November 28, 2	2017-11-28
Isolation scheme for high voltage device Grant 9,673,084 - Liu , et al. June 6, 2	2017-06-06
Isolation Scheme For High Voltage Device App 20160163583 - LIU; Kun ; et al.	2016-06-09
Methods for fabricating integrated circuits with the implantation of fluorine Grant 8,999,803 - Sassiat , et al. April 7, 2	2015-04-07
Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations Grant 8,975,704 - Hoentschel , et al. March 10, 2	2015-03-10
Semiconductor device with reduced contact resistance and method of manufacturing thereof Grant 8,975,708 - Toh , et al. March 10, 2	2015-03-10
Late In-situ Doped Sige Junctions For Pmos Devices On 28 Nm Low Power/high Performance Technologies Using A Silicon Oxide Encapsulation, Early Halo And Extension Implantations App 20150054072 - HOENTSCHEL; Jan ; et al.	2015-02-26
Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations Grant 8,936,977 - Hoentschel , et al. January 20, 2	2015-01-20
Methods for fabricating integrated circuits with the implantation of nitrogen Grant 8,916,430 - Yan , et al. December 23, 2	2014-12-23
Methods For Fabricating Integrated Circuits With The Implantation Of Fluorine App 20140357028 - Sassiat; Nicolas ; et al.	2014-12-04
Methods For Fabricating Integrated Circuits With The Implantation Of Nitrogen App 20140342514 - Yan; Ran ; et al.	2014-11-20
Fluorine-doped Channel Silicon-germanium Layer App 20140264484 - SASSIAT; Nicolas ; et al.	2014-09-18
Methods of tailoring work function of semiconductor devices with high-k/metal layer gate structures by performing a fluorine implant process Grant 8,828,834 - Pandey , et al. September 9, 2	2014-09-09
Middle In-situ Doped Sige Junctions For Pmos Devices On 28 Nm Low Power/high Performance Technologies Using A Silicon Oxide Encapsulation, Early Halo And Extension Implantations App 20140183654 - HOENTSCHEL; Jan ; et al.	2014-07-03
Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations Grant 8,703,578 - Hoentschel , et al. April 22, 2	2014-04-22
Oxygen Free Rta On Gate First Hkmg Stacks App 20140103449 - HOENTSCHEL; Jan ; et al.	2014-04-17
Methods Of Tailoring Work Function Of Semiconductor Devices With High-k/metal Layer Gate Structures By Performing A Fluorine Implant Process App 20130330900 - Pandey; Shesh Mani ; et al.	2013-12-12
Late In-situ Doped Sige Junctions For Pmos Devices On 28 Nm Low Power/high Performance Technologies Using A Silicon Oxide Encapsulation, Early Halo And Extension Implantations App 20130320449 - Hoentschel; Jan ; et al.	2013-12-05
Middle In-situ Doped Sige Junctions For Pmos Devices On 28 Nm Low Power/high Performance Technologies Using A Silicon Oxide Encapsulation, Early Halo And Extension Implantations App 20130320450 - Hoentschel; Jan ; et al.	2013-12-05
Semiconductor Device With Reduced Contact Resistance And Method Of Manufacturing Thereof App 20130270654 - Toh; Eng Huat ; et al.	2013-10-17
Semiconductor device with reduced contact resistance and method of manufacturing thereof Grant 8,470,700 - Toh , et al. June 25, 2	2013-06-25
Methods of forming highly scaled semiconductor devices using a disposable spacer technique Grant 8,440,530 - Hoentschel , et al. May 14, 2	2013-05-14
Methods Of Forming Highly Scaled Semiconductor Devices Using A Disposable Spacer Technique App 20130095620 - Hoentschel; Jan ; et al.	2013-04-18
Nested and isolated transistors with reduced impedance difference Grant 8,143,651 - Widodo , et al. March 27, 2	2012-03-27
Semiconductor device with reduced contact resistance and method of manufacturing thereof App 20120018815 - Toh; Eng Huat ; et al.	2012-01-26
Selective STI stress relaxation through ion implantation Grant 8,008,744 - Teo , et al. August 30, 2	2011-08-30
Nested And Isolated Transistors With Reduced Impedance Difference App 20100301424 - WIDODO; Johnny ; et al.	2010-12-02
Selective Sti Stress Relaxation Through Ion Implantation App 20100230777 - TEO; Lee Wee ; et al.	2010-09-16
Nested and isolated transistors with reduced impedance difference Grant 7,767,577 - Widodo , et al. August 3, 2	2010-08-03
Selective STI stress relaxation through ion implantation Grant 7,727,856 - Teo , et al. June 1, 2	2010-06-01
Nested And Isolated Transistors With Reduced Impedance Difference App 20090206408 - WIDODO; Johnny ; et al.	2009-08-20
Integrated Circuit System Employing Fluorine Doping App 20090090975 - Ong; Shiang Yang ; et al.	2009-04-09
End of range (EOR) secondary defect engineering using chemical vapor deposition (CVD) substitutional carbon doping Grant 7,400,018 - Tan , et al. July 15, 2	2008-07-15
Selective STI Stress Relaxation Through Ion Implantation App 20080150037 - Teo; Lee Wee ; et al.	2008-06-26
End Of Range (eor) Secondary Defect Engineering Using Chemical Vapor Deposition (cvd) Substitutional Carbon Doping App 20060270168 - Tan; Chung Foong ; et al.	2006-11-30
End of range (EOR) secondary defect engineering using substitutional carbon doping Grant 7,109,099 - Tan , et al. September 19, 2	2006-09-19
End of range (EOR) secondary defect engineering using substitutional carbon doping App 20050085055 - Tan, Chung Foong ; et al.	2005-04-21

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