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Patent applications and USPTO patent grants for Ondris; Robert M..The latest application filed is for "clock network architecture".
Patent | Date |
---|---|
Generation of delay values for a simulation model of circuit elements in a clock network Grant 9,639,640 - Savithri , et al. May 2, 2 | 2017-05-02 |
Transceiver for providing a clock signal Grant 9,148,192 - Wong , et al. September 29, 2 | 2015-09-29 |
Clock network architecture Grant 8,937,491 - Gaide , et al. January 20, 2 | 2015-01-20 |
Clock Network Architecture App 20140132305 - Gaide; Brian C. ;   et al. | 2014-05-15 |
Preventing transistor damage Grant 7,564,264 - Morrison , et al. July 21, 2 | 2009-07-21 |
Circuits and methods of using parallel counter controlled delay lines to generate a clock signal Grant 7,535,278 - Ondris , et al. May 19, 2 | 2009-05-19 |
Structure for the main oscillator of a counter-controlled delay line Grant 7,477,112 - Pi , et al. January 13, 2 | 2009-01-13 |
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