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Olarte Gonzalez; Javier Mauricio Patent Filings

Olarte Gonzalez; Javier Mauricio

Patent Applications and Registrations

Patent applications and USPTO patent grants for Olarte Gonzalez; Javier Mauricio.The latest application filed is for "back bias regulator circuit and method therefor".

Company Profile
2.3.3
  • Olarte Gonzalez; Javier Mauricio - Campinas BR
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Back bias regulator circuit and method therefor
Grant 10,394,264 - Coimbra , et al. A
2019-08-27
Back Bias Regulator Circuit And Method Therefor
App 20190250656 - Coimbra; Ricardo Pureza ;   et al.
2019-08-15
Sample-and-hold circuit
Grant 9,997,254 - Vilas Boas , et al. June 12, 2
2018-06-12
Sample And Hold Circuit
App 20180151242 - Vilas Boas; Andre Luis ;   et al.
2018-05-31
Sample and hold circuit
Grant 9,984,763 - Vilas Boas , et al. May 29, 2
2018-05-29
Sample-and-Hold Circuit
App 20180019020 - VILAS BOAS; Andre Luis ;   et al.
2018-01-18

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