Okumura; Naoto

Patent Applications and Registrations

Patent applications and USPTO patent grants for Okumura; Naoto.The latest application filed is for "thiol compound, method for synthesizing same, and uses for said thiol compound".

Company Profile

6.10.9

Okumura; Naoto - Kanagawa JP
OKUMURA; Naoto - Kagawa JP
Okumura, Naoto - Hyogo JP
Okumura; Naoto - Tokyo JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Imaging apparatus and control method Grant 11,438,505 - Okumura , et al. September 6, 2	2022-09-06
Thiol Compound, Method For Synthesizing Same, And Uses For Said Thiol Compound App 20220112330 - OKUMURA; Naoto ; et al.	2022-04-14
Imaging Apparatus And Control Method App 20220030166 - Okumura; Naoto ; et al.	2022-01-27
Epoxy-oxetane compound, method for synthesizing same, and use of said compound Grant 10,913,731 - Aoki , et al. February 9, 2	2021-02-09
Thiol Compounds, Synthesis Method Therefor, And Utilization Of Said Thiol Compounds App 20200369606 - OKUMURA; Naoto ; et al.	2020-11-26
Epoxy-oxetane Compound, Method For Synthesizing Same, And Use Of Said Compound App 20200270236 - AOKI; Kazunori ; et al.	2020-08-27
Mercaptoethylglycol uril compound and utilization thereof Grant 10,550,131 - Matsuda , et al. Fe	2020-02-04
Resin composition Grant 10,246,550 - Iwaya , et al.	2019-04-02
Mercaptoethylglycol Uril Compound And Utilization Thereof App 20180051038 - MATSUDA; Akikazu ; et al.	2018-02-22
Resin Composition App 20180051128 - IWAYA; Kazuki ; et al.	2018-02-22
Azole silane compound, surface treatment solution, surface treatment method, and use thereof Grant 9,688,704 - Miura , et al. June 27, 2	2017-06-27
Azole Silane Compound, Surface Treatment Solution, Surface Treatment Method, And Use Thereof App 20160368935 - MIURA; Shozo ; et al.	2016-12-22
Cache system and cache memory control device controlling cache memory having two access modes App 20040098540 - Itoh, Teruyuki ; et al.	2004-05-20
Integrated circuit device including CMOS tri-state drivers suitable for powerdown Grant 6,566,909 - Okumura May 20, 2	2003-05-20
Integrated circuit device including CMOS tri-state drivers suitable for powerdown App 20010054914 - Okumura, Naoto	2001-12-27
Integrated circuit device including CMOS tri-state drivers suitable for powerdown Grant 6,292,025 - Okumura September 18, 2	2001-09-18
Microprocessor having built-in DRAM and internal data transfer paths wider and faster than independent external transfer paths Grant 6,272,583 - Sakugawa , et al. August 7, 2	2001-08-07
Memory integrated circuit device including a memory having a configuration suitable for mixture with logic Grant 6,130,852 - Ohtani , et al. October 10, 2	2000-10-10
Microcomputer with processor bus having smaller width than memory bus Grant 5,974,493 - Okumura , et al. October 26, 1	1999-10-26

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.