Okazaki; Motoya

Patent Applications and Registrations

Patent applications and USPTO patent grants for Okazaki; Motoya.The latest application filed is for "critical dimensions variance compensation".

Company Profile

1.8.5

Okazaki; Motoya - San Jose CA
Okazaki; Motoya - Tokyo JP
Okazaki; Motoya - Fishkill NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Critical dimensions variance compensation Grant 10,269,663 - Evans , et al.	2019-04-23
Critical Dimensions Variance Compensation App 20180197796 - Evans; Morgan D. ; et al.	2018-07-12
Hydrogenation isomerization catalyst, method for producing same, method for dewaxing hydrocarbon oil, and method for producing lubricant base oil Grant 8,758,596 - Hayasaka , et al. June 24, 2	2014-06-24
Hydrogenation Isomerization Catalyst, Method For Producing Same, Method For Dewaxing Hydrocarbon Oil, And Method For Producing Lubricant Base Oil App 20110270010 - Hayasaka; Kazuaki ; et al.	2011-11-03
Method for generating pattern, method for manufacturing semiconductor device, semiconductor device, and computer program Grant 7,996,813 - Hatano , et al. August 9, 2	2011-08-09
Method for generating pattern, method for manufacturing semiconductor device, semiconductor device, and computer program App 20100115479 - Hatano; Masaaki ; et al.	2010-05-06
Method for generating pattern, method for manufacturing semiconductor device, semiconductor device, and computer program product Grant 7,667,332 - Hatano , et al. February 23, 2	2010-02-23
Simulation circuit pattern evaluation method, manufacturing method of semiconductor integrated circuit, test substrate, and test substrate group Grant 7,308,395 - Kaneko , et al. December 11, 2	2007-12-11
Method for generating pattern, method for manufacturing semiconductor device, semiconductor device, and computer program product App 20060097399 - Hatano; Masaaki ; et al.	2006-05-11
Simulation circuit pattern evaluation method, manufacturing method of semiconductor integrated circuit, test substrate, and test substrate group App 20050075854 - Kaneko, Hisashi ; et al.	2005-04-07
Method of making an integrated circuit with windowed fuse element and contact pad Grant 5,753,539 - Okazaki May 19, 1	1998-05-19
Integrated circuit with windowed fuse element and contact pad Grant 5,550,399 - Okazaki August 27, 1	1996-08-27

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