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Patent applications and USPTO patent grants for Ohsuga; Hiroshi.The latest application filed is for "single-chip microcomputer".
Patent | Date |
---|---|
Single-chip microcomputer App 20120023281 - Kawasaki; Shumpei ;   et al. | 2012-01-26 |
Microcomputer Grant 7,558,944 - Ohsuga , et al. July 7, 2 | 2009-07-07 |
Microcomputer App 20080294873 - Ohsuga; Hiroshi ;   et al. | 2008-11-27 |
Single-chip microcomputer App 20080263228 - Kawasaki; Shumpei ;   et al. | 2008-10-23 |
Microcomputer Grant 7,363,466 - Ohsuga , et al. April 22, 2 | 2008-04-22 |
Microcomputer App 20060224859 - Ohsuga; Hiroshi ;   et al. | 2006-10-05 |
Microcomputer Grant 7,069,423 - Ohsuga , et al. June 27, 2 | 2006-06-27 |
Single-chip microcomputer App 20040199716 - Kawasaki, Shumpei ;   et al. | 2004-10-07 |
Single-chip microcomputer with integral clock generating unit providing clock signals to CPU, internal circuit modules and synchronously controlling external dynamic memory Grant 6,748,507 - Kawasaki , et al. June 8, 2 | 2004-06-08 |
Single-chip microcomputer with hierarchical internal bus structure having data and address signal lines coupling CPU with other processing elements Grant 6,735,683 - Kawasaki , et al. May 11, 2 | 2004-05-11 |
Single-chip microcomputer App 20030233527 - Kawasaki, Shumpei ;   et al. | 2003-12-18 |
Single-chip microcomputer App 20030046514 - Kawasaki, Shumpei ;   et al. | 2003-03-06 |
Microcomputer App 20020184472 - Ohsuga, Hiroshi ;   et al. | 2002-12-05 |
Single-chip microcomputer App 20020007430 - Kawasaki, Shumpei ;   et al. | 2002-01-17 |
Microcomputer system with at least first and second microcomputers each operable in master and slave modes with configurable bus access control terminals and bus use priority controller Grant 6,279,063 - Kawasaki , et al. August 21, 2 | 2001-08-21 |
Microcomputer having multiple bus structure coupling CPU to other processing elements Grant 5,930,523 - Kawasaki , et al. July 27, 1 | 1999-07-27 |
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