Oh; Hwa-Joon

Patent Applications and Registrations

Patent applications and USPTO patent grants for Oh; Hwa-Joon.The latest application filed is for "high speed adder design for a multiply-add based floating point unit".

Company Profile

0.17.23

Oh; Hwa-Joon - Austin TX
Oh; Hwa-Joon - East Lansing MI

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method for controlling rounding modes in single instruction multiple data (SIMD) floating-point units Grant 8,229,989 - Dhong , et al. July 24, 2	2012-07-24
Reducing the latency of sum-addressed shifters Grant 8,166,085 - Dhong , et al. April 24, 2	2012-04-24
High speed adder design for a multiply-add based floating point unit Grant 8,131,795 - Dhong , et al. March 6, 2	2012-03-06
High Speed Adder Design For A Multiply-add Based Floating Point Unit App 20090077155 - Dhong; Sang Hoo ; et al.	2009-03-19
High speed adder design for a multiply-add based floating point unit Grant 7,490,119 - Dhong , et al. February 10, 2	2009-02-10
Method for Controlling Rounding Modes in Single Instruction Multiple Data (SIMD) Floating-Point Units App 20090024684 - Dhong; Sang Hoo ; et al.	2009-01-22
Methods and apparatus for performing multi-value range checks Grant 7,469,265 - Dhong , et al. December 23, 2	2008-12-23
Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units Grant 7,447,725 - Dhong , et al. November 4, 2	2008-11-04
Processor Having Efficient Function Estimate Instructions App 20080263336 - Dhong; Sang Hoo ; et al.	2008-10-23
Apparatus for Reducing the Latency of Sum-Addressed Shifters App 20080195684 - Dhong; Sang Hoo ; et al.	2008-08-14
Processor having efficient function estimate instructions Grant 7,406,589 - Dhong , et al. July 29, 2	2008-07-29
Apparatus and method for reducing the latency of sum-addressed shifters Grant 7,392,270 - Dhong , et al. June 24, 2	2008-06-24
High performance implementation of exponent adjustment in a floating point design Grant 7,290,023 - Dhong , et al. October 30, 2	2007-10-30
Protecting one-hot logic against short-circuits during power-on Grant 7,245,159 - Dhong , et al. July 17, 2	2007-07-17
Leakage current reduction system and method Grant 7,237,163 - Dhong , et al. June 26, 2	2007-06-26
Byte Execution Unit for Carrying Out Byte Instructions in a Processor App 20070061553 - Dhong; Sang Hoo ; et al.	2007-03-15
Byte execution unit for carrying out byte instructions in a processor Grant 7,149,877 - Dhong , et al. December 12, 2	2006-12-12
Processor having efficient function estimate instructions App 20060259745 - Dhong; Sang Hoo ; et al.	2006-11-16
Power saving in FPU with gated power based on opcodes and data Grant 7,137,021 - Dhong , et al. November 14, 2	2006-11-14
Power saving in a floating point unit using a multiplier and aligner bypass Grant 7,058,830 - Dhong , et al. June 6, 2	2006-06-06
Using a leading-sign anticipator circuit for detecting sticky-bit information App 20060101108 - Dhong; Sang Hoo ; et al.	2006-05-11
Leakage current reduction system and method App 20060101315 - Dhong; Sang Hoo ; et al.	2006-05-11
Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units App 20060101107 - Dhong; Sang Hoo ; et al.	2006-05-11
Construction of a folded leading zero anticipator App 20060053190 - Dhong; Sang Hoo ; et al.	2006-03-09
Alignment shifter supporting multiple precisions App 20060031272 - Dhong; Sang Hoo ; et al.	2006-02-09
Apparatus and method for reducing the latency of sum-addressed shifters App 20060026223 - Dhong; Sang Hoo ; et al.	2006-02-02
Protecting one-hot logic against short-curcuits during power-on App 20060012399 - Dhong; Sang Hoo ; et al.	2006-01-19
Fast operand formatting for a high performance multiply-add floating point-unit App 20050228844 - Dhong, Sang H. ; et al.	2005-10-13
Integrated logic and latch design with clock gating at static input signals Grant 6,914,453 - Dhong , et al. July 5, 2	2005-07-05
High speed adder design for a multiply-add based floating point unit App 20050131981 - Dhong, Sang Hoo ; et al.	2005-06-16
High performance implementation of exponent adjustment in a floating point design App 20050114422 - Dhong, Sang Hoo ; et al.	2005-05-26
Methods and apparatus for performing multi-value range checks App 20050086279 - Dhong, Sang Hoo ; et al.	2005-04-21
Byte execution unit for carrying out byte instructions in a processor App 20050015576 - Dhong, Sang Hoo ; et al.	2005-01-20
Integrated logic and latch design with clock gating at static input signals App 20050007152 - Dhong, Sang Hoo ; et al.	2005-01-13
Destructive read architecture for dynamic random access memories Grant 6,829,682 - Kirihata , et al. December 7, 2	2004-12-07
Power saving in FPU with gated power based on opcodes and data App 20040230849 - Dhong, Sang Hoo ; et al.	2004-11-18
Power saving in a floating point unit using a multiplier and aligner bypass App 20040186870 - Dhong, Sang Hoo ; et al.	2004-09-23
Method and apparatus for reducing write operation time in dynamic random access memories App 20020159319 - Kirihata, Toshiaki ; et al.	2002-10-31
Destructive read architecture for dynamic random access memories App 20020161967 - Kirihata, Toshiaki ; et al.	2002-10-31
Modular feedforward neural network architecture with learning Grant 5,689,621 - Salam , et al. November 18, 1	1997-11-18

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