| Patent | Date |
|---|
Semiconductor IC device having a RAM interposed between different logic sections and by-pass signal lines extending over the RAM for mutually connecting the logic sections
Grant 5,477,067 - Isomura , et al. * December 19, 1 | 1995-12-19 |
Method of manufacturing semiconductor integrated circuit device
Grant 5,354,699 - Ikeda , et al. October 11, 1 | 1994-10-11 |
Semiconductor integrated circuit device having a gate array with a ram and by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array
Grant 5,243,208 - Isomura , et al. * September 7, 1 | 1993-09-07 |
Semiconductor integrated circuit device forming on a common substrate MISFETs isolated by a field oxide and bipolar transistors isolated by a groove
Grant 5,214,302 - Uchida , et al. May 25, 1 | 1993-05-25 |
Semiconductor memory system for use in logic LSI's
Grant 5,117,390 - Akimoto , et al. May 26, 1 | 1992-05-26 |
Semiconductor integrated circuit device having a gate array with a RAM and by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array
Grant 5,103,282 - Isomura , et al. * April 7, 1 | 1992-04-07 |
Method of fabricating a semiconductor substrate, and semiconductor device, having thick oxide films and groove isolation
Grant 5,084,402 - Uchida , et al. * January 28, 1 | 1992-01-28 |
Semiconductor integrated circuit device
Grant 5,057,894 - Ikeda , et al. October 15, 1 | 1991-10-15 |
Semiconductor memory system for use in logic LSI's
Grant 5,023,835 - Akimoto , et al. June 11, 1 | 1991-06-11 |
Semiconductor device for a ram disposed on chip so as to minimize distances of signal paths between the logic circuits and memory circuit
Grant 5,014,242 - Akimoto , et al. May 7, 1 | 1991-05-07 |
Semiconductor integrated circuit device
Grant 4,959,704 - Isomura , et al. September 25, 1 | 1990-09-25 |
Semiconductor integrated circuit with dummy pedestals
Grant 4,949,162 - Tamaki , et al. August 14, 1 | 1990-08-14 |
Semiconductor integrated circuit
Grant 4,858,189 - Ogiue , et al. August 15, 1 | 1989-08-15 |
Method for fabricating a semiconductor integrated circuit device having thick oxide films and groove etch and refill
Grant 4,853,343 - Uchida , et al. August 1, 1 | 1989-08-01 |
MOS/bipolar device with stepped buried layer under active regions
Grant 4,799,098 - Ikeda , et al. January 17, 1 | 1989-01-17 |
Isolation regions formed by locos followed with groove etch and refill
Grant 4,746,963 - Uchida , et al. May 24, 1 | 1988-05-24 |
Semiconductor integrated circuit
Grant 4,713,796 - Ogiue , et al. December 15, 1 | 1987-12-15 |
Packaged semiconductor device structure including getter material for decreasing gas from a protective organic covering
Grant 4,630,095 - Otsuka , et al. December 16, 1 | 1986-12-16 |
Method of making semiconductor integrated circuit device
Grant 4,219,369 - Ogiue , et al. August 26, 1 | 1980-08-26 |
Complementary MIS integrated circuit device on insulating substrate
Grant 3,893,155 - Ogiue July 1, 1 | 1975-07-01 |
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