Obradovic; Borna

Patent Applications and Registrations

Patent applications and USPTO patent grants for Obradovic; Borna.The latest application filed is for "horizontal nanosheet fets and methods of manufacturing the same".

Company Profile

1.24.29

Obradovic; Borna - Leander TX
Obradovic; Borna - McKinney TX US
Obradovic; Borna - Hillsboro OR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
FinFet having dual vertical spacer and method of manufacturing the same Grant 10,181,527 - Palle , et al. Ja	2019-01-15
Horizontal nanosheet FETs and methods of manufacturing the same Grant 9,960,232 - Obradovic , et al. May 1, 2	2018-05-01
Method to make self-aligned vertical field effect transistor Grant 9,899,529 - Hong , et al. February 20, 2	2018-02-20
Methods of forming nanosheets on lattice mismatched substrates Grant 9,870,940 - Wang , et al. January 16, 2	2018-01-16
Field effect transistor with stacked nanowire-like channels and methods of manufacturing the same Grant 9,853,114 - Rodder , et al. December 26, 2	2017-12-26
Horizontal Nanosheet Fets And Methods Of Manufacturing The Same App 20170323941 - Obradovic; Borna ; et al.	2017-11-09
Zero leakage, high noise margin coupled giant spin hall based retention latch Grant 9,805,795 - Rakshit , et al. October 31, 2	2017-10-31
Vertical field effect transistor with biaxial stressor layer Grant 9,773,904 - Obradovic , et al. September 26, 2	2017-09-26
Zero Leakage, High Noise Margin Coupled Giant Spin Hall Based Retention Latch App 20170200499 - Rakshit; Titash ; et al.	2017-07-13
S/D connection to individual channel layers in a nanosheet FET Grant 9,653,287 - Rodder , et al. May 16, 2	2017-05-16
Method To Make Self-aligned Vertical Field Effect Transistor App 20170133513 - Hong; Joon Goo ; et al.	2017-05-11
Thermionically-overdriven tunnel FETs and methods of fabricating the same Grant 9,647,098 - Obradovic , et al. May 9, 2	2017-05-09
Finfet Having Dual Vertical Spacer And Method Of Manufacturing The Same App 20170110568 - Palle; Dharmendar Reddy ; et al.	2017-04-20
Vertical Field Effect Transistor with Biaxial Stressor Layer App 20170077304 - Obradovic; Borna ; et al.	2017-03-16
Methods of Forming Nanosheets on Lattice Mismatched Substrates App 20170040209 - Wang; Wei-E ; et al.	2017-02-09
S/d Connection To Individual Channel Layers In A Nanosheet Fet App 20160126310 - RODDER; Mark ; et al.	2016-05-05
Multiple Cpp For Increased Source/drain Area For Fets Including In A Critical Speed Path App 20160111421 - RODDER; Mark S. ; et al.	2016-04-21
Integrated circuits with Si and non-Si nanosheet FET co-integration with low band-to-band tunneling and methods of fabricating the same Grant 9,287,357 - Rodder , et al. March 15, 2	2016-03-15
Thermionically-overdriven Tunnel Fets And Methods Of Fabricating The Same App 20160020305 - Obradovic; Borna ; et al.	2016-01-21
Integrated Circuits with Si and Non-Si Nanosheet FET Co-Integration with Low Band-to-Band Tunneling and Methods of Fabricating the Same App 20150364542 - RODDER; Mark S. ; et al.	2015-12-17
Multiple Channel Length Finfets with Same Physical Gate Length App 20150318282 - Rodder; Mark S. ; et al.	2015-11-05
Modeling of ferroelectric capacitors to include local statistical variations of ferroelectric properties Grant 8,380,476 - Obradovic , et al. February 19, 2	2013-02-19
Ferroelectric Memory Electrical Contact App 20120168837 - BARTLING; Steven Craig ; et al.	2012-07-05
Characterization and modeling of ferroelectric capacitors Grant 8,170,858 - Obradovic , et al. May 1, 2	2012-05-01
Mitigation of gate to contact capacitance in CMOS flow Grant 8,119,470 - Ekbote , et al. February 21, 2	2012-02-21
Differential poly doping and circuits therefrom Grant 8,114,729 - Ekbote , et al. February 14, 2	2012-02-14
Modeling of Non-Quasi-Static Effects During Hot Carrier Injection Programming of Non-Volatile Memory Cells App 20110282639 - Obradovic; Borna ; et al.	2011-11-17
Method to improve transistor tox using SI recessing with no additional masking steps Grant 7,892,930 - Obradovic , et al. February 22, 2	2011-02-22
Method To Improve Transistor Tox Using Si Recessing With No Additional Masking Steps App 20110027954 - Obradovic; Borna ; et al.	2011-02-03
Modeling of Ferroelectric Capacitors to Include Local Statistical Variations of Ferroelectric Properties App 20100299115 - Obradovic; Borna ; et al.	2010-11-25
MOS device and process having low resistance silicide interface using additional source/drain implant Grant 7,812,401 - Obradovic , et al. October 12, 2	2010-10-12
Characterization and Modeling of Ferroelectric Capacitors App 20100174513 - Obradovic; Borna ; et al.	2010-07-08
Method to improve transistor Tox using high-angle implants with no additional masks Grant 7,727,838 - Obradovic , et al. June 1, 2	2010-06-01
CD gate bias reduction and differential N+ poly doping for CMOS circuits Grant 7,718,482 - Ekbote , et al. May 18, 2	2010-05-18
Mos Device And Process Having Low Resistance Silicide Interface Using Additional Source/drain Implant App 20100109089 - OBRADOVIC; Borna ; et al.	2010-05-06
MOS device and process having low resistance silicide interface using additional source/drain implant Grant 7,682,892 - Obradovic , et al. March 23, 2	2010-03-23
Semiconductor doping with improved activation Grant 7,572,716 - Bu , et al. August 11, 2	2009-08-11
Differential offset spacer Grant 7,537,988 - Ekbote , et al. May 26, 2	2009-05-26
Differential Poly Doping And Circuits Therefrom App 20090096031 - EKBOTE; Shashank ; et al.	2009-04-16
Cd Gate Bias Reduction And Differential N+ Poly Doping For Cmos Circuits App 20090098694 - Ekbote; Shashank ; et al.	2009-04-16
Differential Offset Spacer App 20090098695 - Ekbote; Shashank ; et al.	2009-04-16
Method To Improve Transistor Tox Using Si Recessing With No Additional Masking Steps App 20090093095 - Obradovic; Borna ; et al.	2009-04-09
Mos Device And Process Having Low Resistance Silicide Interface Using Additional Source/drain Implant App 20090057759 - Obradovic; Borna ; et al.	2009-03-05
Method To Improve Transistor Tox Using High-angle Implants With No Additional Masks App 20090029516 - Obradovic; Borna ; et al.	2009-01-29
Semiconductor Doping With Improved Activation App 20080268623 - Bu; Haowen ; et al.	2008-10-30
Mitigation of gate to contact capacitance in CMOS flow App 20080230815 - Ekbote; Shashank Sureshchandra ; et al.	2008-09-25
Methods of forming stress enhanced PMOS structures App 20060226453 - Wang; Everett X. ; et al.	2006-10-12
Method and structure to decrease area capacitance within a buried insulator device Grant 7,091,560 - Stettler , et al. August 15, 2	2006-08-15
Method and structure to decrease area capacitance within a buried insulator device App 20050130379 - Stettler, Mark A. ; et al.	2005-06-16
Method to form a structure to decrease area capacitance within a buried insulator device Grant 6,867,104 - Stettler , et al. March 15, 2	2005-03-15
Method and structure to decrease area capacitance within a buried insulator device App 20040124467 - Stettler, Mark A. ; et al.	2004-07-01

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