| Patent | Date |
|---|
System and method for computational transport network-on-chip (NoC)
Grant 11,082,327 - Nye August 3, 2 | 2021-08-03 |
Systems and methods for mixed instruction multiple data (xIMD) computing
Grant 10,990,394 - Nye April 27, 2 | 2021-04-27 |
SYSTEM AND METHOD FOR COMPUTATIONAL TRANSPORT NETWORK-ON-CHIP (NoC)
App 20200213217 - NYE; Jeffrey L. | 2020-07-02 |
Live migration of hardware accelerated applications
Grant 10,489,193 - Nye , et al. Nov | 2019-11-26 |
Live Migration Of Hardware Accelerated Applications
App 20190129744 - Nye; Jeffrey L. ; et al. | 2019-05-02 |
SYSTEMS AND METHODS FOR MIXED INSTRUCTION MULTIPLE DATA (xIMD) COMPUTING
App 20190095208 - Nye; Jeffrey L. | 2019-03-28 |
Live migration of hardware accelerated applications
Grant 10,169,065 - Nye , et al. J | 2019-01-01 |
Integrated circuit with control node circuitry and processing circuitry
Grant 9,552,206 - Johnson , et al. January 24, 2 | 2017-01-24 |
High-performance, Scalable Mutlicore Hardware And Software System
App 20120131309 - Johnson; William M. ; et al. | 2012-05-24 |
Processes, circuits, devices, and systems for branch prediction and other processor improvements
Grant 7,752,426 - Nye , et al. July 6, 2 | 2010-07-06 |
Full/selector output from one of plural flag generation count outputs
Grant 7,587,532 - Nye , et al. September 8, 2 | 2009-09-08 |
Cache lock mechanism with speculative allocation
Grant 7,266,648 - Sutanto , et al. September 4, 2 | 2007-09-04 |
Multi-core Architecture With Hardware Messaging
App 20070180310 - Johnson; William M. ; et al. | 2007-08-02 |
Method and apparatus for adaptive buffer sizing
App 20060179186 - Nye; Jeffrey L. ; et al. | 2006-08-10 |
Processes, circuits, devices, and systems for branch prediction and other processor improvements
App 20060095750 - Nye; Jeffrey L. ; et al. | 2006-05-04 |
Cache lock mechanism with speculative allocation
App 20060064551 - Sutanto; Edwin R. ; et al. | 2006-03-23 |
Cache lock mechanism with speculative allocation
Grant 6,986,010 - Sutanto , et al. January 10, 2 | 2006-01-10 |
Cache lock mechanism with speculative allocation
App 20040117573 - Sutanto, Edwin R. ; et al. | 2004-06-17 |
Two computer access circuit using address translation into common register file
Grant 6,189,077 - Robertson , et al. February 13, 2 | 2001-02-13 |
Multifunctional access devices, systems and methods
Grant 6,154,824 - Robertson , et al. November 28, 2 | 2000-11-28 |
Using prioritized interrupt callback routines to process different types of multimedia information
Grant 5,940,610 - Baker , et al. August 17, 1 | 1999-08-17 |
Graphics processor writing to shadow register at predetermined address simultaneously with writing to control register
Grant 5,696,923 - Robertson , et al. December 9, 1 | 1997-12-09 |
Memory access circuit with address translation performing auto increment of translated address on writes and return to translated address on reads
Grant 5,696,924 - Robertson , et al. December 9, 1 | 1997-12-09 |
Multifunctional access devices, systems and methods
Grant 5,546,553 - Robertson , et al. August 13, 1 | 1996-08-13 |
Data cache access for signal processing systems
Grant 5,386,538 - Nye January 31, 1 | 1995-01-31 |
Controlled delay devices, systems and methods
Grant 5,293,468 - Nye , et al. March 8, 1 | 1994-03-08 |
Graphics systems, palettes and methods with combined video and shift clock control
Grant 5,287,100 - Guttag , et al. February 15, 1 | 1994-02-15 |
Memory mapped interface between host computer and graphics system
Grant 5,280,579 - Nye January 18, 1 | 1994-01-18 |
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