Nowka; Kevin J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Nowka; Kevin J..The latest application filed is for "test structure for characterizing multi-port static random access memory and register file arrays".

Company Profile

0.32.27

Nowka; Kevin J. - Georgetown TX
Nowka; Kevin J. - Round Rock TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Test structure for characterizing multi-port static random access memory and register file arrays Grant 8,555,119 - Chang , et al. October 8, 2	2013-10-08
System and method for implementing simplified arithmetic logic unit processing of value-based control dependence sequences Grant 8,285,765 - Chen , et al. October 9, 2	2012-10-09
Test structure for characterizing multi-port static random access memory and register file arrays Grant 8,261,138 - Chang , et al. September 4, 2	2012-09-04
Test Structure For Characterizing Multi-port Static Random Access Memory And Register File Arrays App 20120212997 - Chang; Leland ; et al.	2012-08-23
Static pulsed bus circuit and method having dynamic power supply rail selection Grant 7,882,370 - Deogun , et al. February 1, 2	2011-02-01
Optimizing SRAM performance over extended voltage or process range using self-timed calibration of local clock generator Grant 7,864,625 - Carpenter , et al. January 4, 2	2011-01-04
Wordline-to-bitline output timing ring oscillator circuit for evaluating storage array performance Grant 7,760,565 - Kuang , et al. July 20, 2	2010-07-20
Optimizing Sram Performance over Extended Voltage or Process Range Using Self-Timed Calibration of Local Clock Generator App 20100085823 - Carpenter; Gary D. ; et al.	2010-04-08
Storage array including a local clock buffer with programmable timing Grant 7,668,037 - Carpenter , et al. February 23, 2	2010-02-23
Pulsed ring oscillator circuit for storage cell read timing evaluation Grant 7,620,510 - Carpenter , et al. November 17, 2	2009-11-17
Digital circuit with dynamic power and performance control via per-block selectable operating voltage Grant 7,564,259 - Agarwal , et al. July 21, 2	2009-07-21
Method for evaluating memory cell performance Grant 7,545,690 - Kuang , et al. June 9, 2	2009-06-09
Storage Array Including a Local Clock Buffer with Programmable Timing App 20090116312 - Carpenter; Gary D. ; et al.	2009-05-07
Wordline-To-Bitline Output Timing Ring Oscillator Circuit for Evaluating Storage Array Performance App 20090027065 - Kuang; Jente B. ; et al.	2009-01-29
Pulsed Ring Oscillator Circuit For Storage Cell Read Timing Evaluation App 20080225615 - Carpenter; Gary D. ; et al.	2008-09-18
Pulsed ring oscillator circuit for storage cell read timing evaluation Grant 7,409,305 - Carpenter , et al. August 5, 2	2008-08-05
Test Structure for Characterizing Multi-Port Static Random Access Memory and Register File Arrays App 20080155362 - Chang; Leland ; et al.	2008-06-26
Partial Data Flow Functional Gating Using Structural Or Partial Operand Value Information App 20080141046 - Chen; Lei ; et al.	2008-06-12
System and Method for Implementing Simplified Arithmetic Logic Unit Processing of Value-Based Control Dependence Sequences App 20080141006 - Chen; Lei ; et al.	2008-06-12
Method For Evaluating Memory Cell Performance App 20080130387 - Kuang; Jente B. ; et al.	2008-06-05
Cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance Grant 7,349,271 - Kuang , et al. March 25, 2	2008-03-25
Static Pulsed Bus Circuit and Method Having Dynamic Power Supply Rail Selection App 20080069558 - Deogun; Harmander Singh ; et al.	2008-03-20
Dual-gate dynamic logic circuit with pre-charge keeper Grant 7,298,176 - Ngo , et al. November 20, 2	2007-11-20
Cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance App 20070237012 - Kuang; Jente B. ; et al.	2007-10-11
Power-gating cell for virtual power rail control Grant 7,276,932 - Kuang , et al. October 2, 2	2007-10-02
Dynamic leakage control circuit Grant 7,266,707 - Ngo , et al. September 4, 2	2007-09-04
Digital circuit with dynamic power and performance control via per-block selectable operating voltage App 20070200593 - Agarwal; Kanak B. ; et al.	2007-08-30
Dual-gate dynamic logic circuit with pre-charge keeper App 20070040584 - Ngo; Hung C. ; et al.	2007-02-22
Voltage controlled oscillator using dual gated asymmetrical FET devices App 20070040621 - Ngo; Hung C. ; et al.	2007-02-22
Controlled load limited switch dynamic logic circuitry Grant 7,129,754 - Ngo , et al. October 31, 2	2006-10-31
Controlled Load Limited Switch Dynamic Logic Circuitry App 20060208763 - Ngo; Hung C. ; et al.	2006-09-21
Circuit for controlling leakage Grant 7,061,265 - Ngo , et al. June 13, 2	2006-06-13
Interface circuit for coupling between logic circuit domains Grant 7,046,063 - Kuang , et al. May 16, 2	2006-05-16
Power-gating cell for virtual power rail control App 20060055391 - Kuang; Jente B. ; et al.	2006-03-16
Dynamic leakage control circuit App 20060059376 - Ngo; Hung C. ; et al.	2006-03-16
Circuit for controlling leakage App 20060033531 - Ngo; Hung C. ; et al.	2006-02-16
Self limiting gate leakage driver Grant 6,980,018 - Ngo , et al. December 27, 2	2005-12-27
Buffer/driver circuits Grant 6,975,134 - Kuang , et al. December 13, 2	2005-12-13
Self Limiting Gate Leakage Driver App 20050242840 - Ngo, Hung C. ; et al.	2005-11-03
Interface circuit for coupling between logic circuit domains App 20050225355 - Kuang, Jente B. ; et al.	2005-10-13
Buffer/driver Circuits App 20050225352 - Kuang, Jente B. ; et al.	2005-10-13
Low gate-leakage virtual rail circuit Grant 6,872,991 - Ngo , et al. March 29, 2	2005-03-29
Multi-mode VCO Grant 6,809,602 - Boerstler , et al. October 26, 2	2004-10-26
Technique for mitigating gate leakage during a sleep state Grant 6,791,361 - Alon , et al. September 14, 2	2004-09-14
Pre-reduction technique within a multiplier/accumulator architecture Grant 6,763,367 - Kwon , et al. July 13, 2	2004-07-13
Low power low voltage transistor--transistor logic I/O driver Grant 6,753,698 - Carpenter , et al. June 22, 2	2004-06-22
Technique for mitigating gate leakage during a sleep state App 20040113657 - Alon, Elad ; et al.	2004-06-17
Low power low voltage transistor-transistor logic I/O driver App 20040027163 - Carpenter, Gary D. ; et al.	2004-02-12
Method and apparatus for performing rotate operations using cascaded multiplexers Grant 6,675,182 - Hofstee , et al. January 6, 2	2004-01-06
Method and apparatus for testing pipelined dynamic logic Grant 6,636,996 - Nowka October 21, 2	2003-10-21
Pre-reduction technique within a multiplier/accumulator architecture App 20030158879 - Kwon, Ohsang ; et al.	2003-08-21
Body-contacted And Double Gate-contacted Differential Logic Circuit And Method Of Operation App 20030112035 - Bernstein, Kerry ; et al.	2003-06-19
Multi-mode VCO App 20030071691 - Boerstler, David W. ; et al.	2003-04-17
Dual mode charge pump Grant 6,529,082 - Boerstler , et al. March 4, 2	2003-03-04
Dynamically scalable low voltage clock generation system Grant 6,515,530 - Boerstler , et al. February 4, 2	2003-02-04
Glitch-less clock selector Grant 6,501,304 - Boerstler , et al. December 31, 2	2002-12-31
Clock divider with bypass and stop clock Grant 6,483,888 - Boerstler , et al. November 19, 2	2002-11-19
Method and apparatus for testing pipelined dynamic logic App 20020069384 - Nowka, Kevin J.	2002-06-06