loadpatents
Patent applications and USPTO patent grants for Novof; Ilya I..The latest application filed is for "delay equalization apparatus and method".
Patent | Date |
---|---|
Delay equalization apparatus and method Grant 5,825,226 - Ferraiolo , et al. October 20, 1 | 1998-10-20 |
Anti-latching mechanism for phase lock loops Grant 5,694,087 - Ferraiolo , et al. December 2, 1 | 1997-12-02 |
Integrated compact capacitor-resistor/inductor configuration Grant 5,541,442 - Keil , et al. July 30, 1 | 1996-07-30 |
Charge pump circuit with symmetrical current output for phase-controlled loop system Grant 5,508,660 - Gersbach , et al. April 16, 1 | 1996-04-16 |
Differential current controlled oscillator with variable load Grant 5,495,207 - Novof February 27, 1 | 1996-02-27 |
Method and apparatus for reducing jitter in a phase locked loop circuit Grant 5,491,439 - Kelkar , et al. February 13, 1 | 1996-02-13 |
Fast communication link bit error rate estimator Grant 5,418,789 - Gersbach , et al. May 23, 1 | 1995-05-23 |
Digital voltage controlled oscillator Grant 5,347,234 - Gersbach , et al. September 13, 1 | 1994-09-13 |
Adaptive equalization and regeneration system Grant 5,293,405 - Gersbach , et al. March 8, 1 | 1994-03-08 |
Clock signal latency elimination network Grant 5,272,729 - Bechade , et al. December 21, 1 | 1993-12-21 |
Phase and frequency adjustable digital phase lock logic system Grant 5,245,637 - Gersbach , et al. September 14, 1 | 1993-09-14 |
Digital data link performance monitor Grant 5,220,581 - Ferraiolo , et al. June 15, 1 | 1993-06-15 |
Data edge phase sorting circuits Grant 5,212,716 - Ferraiolo , et al. May 18, 1 | 1993-05-18 |
Digital integrating clock extractor Grant 5,185,768 - Ferraiolo , et al. February 9, 1 | 1993-02-09 |
Digital data regeneration and deserialization circuits Grant 5,101,203 - Gersbach , et al. March 31, 1 | 1992-03-31 |
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