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Communicating via a mailbox interface of a processor
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System, Apparatus And Method For Probeless Field Scan Of A Processor
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Supporting Hang Detection And Data Recovery In Microprocessor Systems
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Device, System And Method To Facilitate Disaster Recovery For A Multi-processor Platform
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Cache Behavior For Secure Memory Repartitioning Systems
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Systems and methods for enhancing BIOS performance by alleviating code-size limitations
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Core-Only System Management Interrupt
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Pipelined prefetcher for parallel advancement of multiple data streams
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Communicating Via A Mailbox Interface Of A Processor
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Apparatus and method for memory-hierarchy aware producer-consumer instruction
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Systems And Methods For Enhancing Bios Performance By Alleviating Code-size Limitations
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Pipelined Prefetcher for Parallel Advancement Of Multiple Data Streams
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Masking a power state of a core of a processor
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Adaptive hierarchical cache policy in a microprocessor
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Masking A Power State Of A Core Of A Processor
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Adaptive Hierarchical Cache Policy In A Microprocessor
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Restricting clock signal delivery in a processor
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Method and apparatus for cache line write back operation
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Instruction and Logic for Speculative Request Support for Prefetching
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Apparatus and method for implement a multi-level memory hierarchy
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Communicating Via A Mailbox Interface Of A Processor
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Adaptive hierarchical cache policy in a microprocessor
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Cache circuit having a tag array with smaller latency than a data array
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Reduced power mode of a cache unit
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Apparatus and Method to Transfer Data Packets between Domains of a Processor
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Method And Apparatus For Cache Line Write Back Operation
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Multi latency configurable cache
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Method and apparatus for error correction in a cache
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Restricting Clock Signal Delivery In A Processor
App 20140380081 - Gendler; Alexander ; et al. | 2014-12-25 |
Reduced Power Mode Of A Cache Unit
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Apparatus And Method For Implement A Multi-level Memory Hierarchy
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Adaptive Hierarchical Cache Policy In A Microprocessor
App 20140281239 - Novakovsky; Larisa ; et al. | 2014-09-18 |
Multi Latency Configurable Cache
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Cache Circuit Having A Tag Array With Smaller Latency Than A Data Array
App 20140208035 - Novakovsky; Larisa | 2014-07-24 |
Apparatus And Method For Memory-hierarchy Aware Producer-consumer Instructions
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Apparatus And Method For Memory-hierarchy Aware Producer-consumer Instruction
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Method And Apparatus For Error Correction In A Cache
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Cache Memory Staged Reopen
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Apparatus And Method For Dynamically Managing Memory Access Bandwidth In Multi-core Processor
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Posting weakly ordered transactions
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Device, system and method of managing a resource request
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Posting Weakly Ordered Transactions
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Device, system and method of managing a resource request
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