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name:-0.014487028121948
name:-0.010799884796143
name:-0.00049996376037598
Nouri; Faran Patent Filings

Nouri; Faran

Patent Applications and Registrations

Patent applications and USPTO patent grants for Nouri; Faran.The latest application filed is for "nmos transistor devices and methods for fabricating same".

Company Profile
0.10.12
  • Nouri; Faran - Los Altos CA
  • Nouri; Faran - Las Altos CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
NMOS transistor devices and methods for fabricating same
Grant 8,330,225 - Thirupapuliyur , et al. December 11, 2
2012-12-11
Methods for forming a transistor and modulating channel stress
Grant 8,105,908 - Thirupapuliyur , et al. January 31, 2
2012-01-31
Nmos Transistor Devices And Methods For Fabricating Same
App 20110278651 - Thirupapuliyur; Sunderraj ;   et al.
2011-11-17
NMOS transistor devices and methods for fabricating same
Grant 7,994,015 - Thirupapuliyur , et al. August 9, 2
2011-08-09
Methods for forming a transistor
Grant 7,968,413 - Nouri , et al. June 28, 2
2011-06-28
Methods for forming a transistor
Grant 7,833,869 - Nouri , et al. November 16, 2
2010-11-16
Nmos Transistor Devices And Methods For Fabricating Same
App 20100264470 - THIRUPAPULIYUR; SUNDERRAJ ;   et al.
2010-10-21
Methods for contact resistance reduction of advanced CMOS devices
Grant 7,795,124 - Nouri , et al. September 14, 2
2010-09-14
Method of forming a silicon oxynitride layer
Grant 7,569,502 - Olsen , et al. August 4, 2
2009-08-04
Methods For Forming A Transistor
App 20080299735 - NOURI; FARAN ;   et al.
2008-12-04
Methods For Forming A Transistor
App 20080280413 - Nouri; Faran ;   et al.
2008-11-13
Methods for forming a transistor
Grant 7,413,957 - Nouri , et al. August 19, 2
2008-08-19
Methods For Contact Resistance Reduction Of Advanced Cmos Devices
App 20070298575 - Nouri; Faran ;   et al.
2007-12-27
CMOS S/D SiGe DEVICE MADE WITH ALTERNATIVE INTEGRATION PROCESS
App 20070284668 - Shen; Meihua ;   et al.
2007-12-13
ALTERNATIVE INTEGRATION SCHEME FOR CMOS S/D SiGe PROCESS
App 20070287244 - Shen; Meihua ;   et al.
2007-12-13
Method Of Forming A Silicon Oxynitride Layer
App 20070087583 - OLSEN; CHRISTOPHER ;   et al.
2007-04-19
Methods for forming a transistor and creating channel stress
App 20060289900 - Thirupapuliyur; Sunderraj ;   et al.
2006-12-28
Silicon nitride film with stress control
App 20060009041 - Iyer; R. Suryanarayanan ;   et al.
2006-01-12
Methods for forming a transistor
App 20050287752 - Nouri, Faran ;   et al.
2005-12-29
Method of forming a silicon oxynitride layer
App 20050130448 - Olsen, Christopher ;   et al.
2005-06-16
Method of manufacturing shallow source/drain junctions in a salicide process
Grant 6,274,445 - Nouri August 14, 2
2001-08-14
Method for eliminating stress induced dislocations in CMOS devices
Grant 6,221,735 - Manley , et al. April 24, 2
2001-04-24

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