Norwood; Roger D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Norwood; Roger D..The latest application filed is for "apparatuses and methods for address detection".

Company Profile

0.17.4

Norwood; Roger D. - McKinney TX
Norwood; Roger D. - Sugar Land TX
Norwood; Roger D. - Houston TX
Norwood; Roger D. - Stafford TX
Norwood; Roger D. - Sugarland TX
Norwood; Roger D. - Sunnyvale CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Apparatuses and methods for address detection Grant 11,217,295 - Mazumder , et al. January 4, 2	2022-01-04
Apparatuses And Methods For Address Detection App 20200042423 - Mazumder; Kallol ; et al.	2020-02-06
Apparatuses and methods for address detection Grant 10,534,686 - Mazumder , et al. Ja	2020-01-14
Apparatuses And Methods For Address Detection App 20150213872 - Mazumder; Kallol ; et al.	2015-07-30
Asynchronous interface circuit and method for a pseudo-static memory device Grant 7,106,637 - Lovett , et al. September 12, 2	2006-09-12
Asynchronous interface circuit and method for a pseudo-static memory device App 20040141397 - Lovett, Simon J. ; et al.	2004-07-22
Asynchronous interface circuit and method for a pseudo-static memory device Grant 6,690,606 - Lovett , et al. February 10, 2	2004-02-10
Asynchronous interface circuit and method for a pseudo-static memory device App 20030179612 - Lovett, Simon J. ; et al.	2003-09-25
High-speed memory arranged for operating synchronously with a microprocessor Grant 6,088,280 - Vogley , et al. July 11, 2	2000-07-11
Clock skew circuit Grant 6,049,241 - Brown , et al. April 11, 2	2000-04-11
Random access memory with latency arranged for operating synchronously with a micro processor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock Grant 5,808,958 - Vogley , et al. September 15, 1	1998-09-15
Random access memory arranged for operating synchronously with a microprocessor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock Grant 5,587,954 - Vogley , et al. December 24, 1	1996-12-24
Interface level programmability Grant 5,557,219 - Norwood , et al. September 17, 1	1996-09-17
System including a data processor, a synchronous dram, a peripheral device, and a system clock Grant 5,390,149 - Vogley , et al. February 14, 1	1995-02-14
Method and apparatus for inhibiting a predecoder when selecting a redundant row line Grant 5,327,380 - Kersh, III , et al. July 5, 1	1994-07-05
Method for generating power-up pulse Grant 5,203,867 - Love , et al. * April 20, 1	1993-04-20
Distributed signal transmission to an integrated circuit array Grant 4,969,123 - Norwood , et al. November 6, 1	1990-11-06
Glitch suppression circuit Grant 4,965,474 - Childers , et al. October 23, 1	1990-10-23
High speed, low-power nibble mode circuitry for dynamic memory Grant 4,685,089 - Patel , et al. August 4, 1	1987-08-04
Semiconductor dynamic memory device with decoded active loads Grant 4,656,613 - Norwood , et al. April 7, 1	1987-04-07
Semiconductor dynamic memory device with multiplexed sense amplifier and write-activated active loads Grant 4,636,987 - Norwood , et al. January 13, 1	1987-01-13

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