North American Philips Corp., Signetics Division

Patent Applications and Registrations

Patent applications and USPTO patent grants for North American Philips Corp., Signetics Division.The latest application filed is for "method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material".

Company Profile

0.18.0

North American Philips Corp., Signetics Division - Sunnyvale CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material Grant 5,063,175 - Broadbent November 5, 1	1991-11-05
Use of venting slots to improve hermetic seal for semiconductor dice housed in ceramic packages Grant 5,059,558 - Tatsanakit , et al. October 22, 1	1991-10-22
Semiconductor fabrication process using sacrificial oxidation to reduce tunnel formation during tungsten deposition Grant 5,021,358 - Flanner , et al. June 4, 1	1991-06-04
Fabrication method using oxidation to control size of fusible link Grant 5,015,604 - Lim , et al. May 14, 1	1991-05-14
Transistor manufacturing process using three-step base doping Grant 5,006,476 - De Jong , et al. April 9, 1	1991-04-09
Circuit for synchronizing transitions of bits in a digital code Grant 4,939,517 - Baltus , et al. July 3, 1	1990-07-03
Differential amplifier using voltage level shifting to achieve rail-to-rail input capability at very low power supply voltage Grant 4,918,398 - Huijsing , et al. April 17, 1	1990-04-17
Complementary voltage interpolation circuit with transmission delay compensation Grant 4,897,656 - van de Plassche , et al. January 30, 1	1990-01-30
Error correction circuit suitable for thermometer or circular code Grant 4,870,417 - van de Plassche , et al. September 26, 1	1989-09-26
Complementary voltage interpolation circuit Grant 4,831,379 - van de Plassche May 16, 1	1989-05-16
Self-aligned metallization for semiconductor device and process using selectively deposited tungsten Grant 4,822,749 - Flanner , et al. April 18, 1	1989-04-18
Schottky-type rectifier having controllable barrier height Grant 4,816,879 - Ellwanger March 28, 1	1989-03-28
Stabilized current and voltage reference sources Grant 4,816,742 - van de Plassche March 28, 1	1989-03-28
Method of fabrication of semiconductor device having a planar configuration Grant 4,803,173 - Sill , et al. February 7, 1	1989-02-07
Method of fabricating field-effect transistor utilizing improved gate sidewall spacers Grant 4,786,609 - Chen November 22, 1	1988-11-22
Field-programmable device with buffer between programmable circuit Grant 4,783,763 - Bergman November 8, 1	1988-11-08
Switching device with dynamic hysteresis Grant 4,740,717 - Fletcher , et al. April 26, 1	1988-04-26
Code converter with complementary output voltages Grant 4,737,766 - van de Plassche April 12, 1	1988-04-12

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.