loadpatents
name:-0.012327909469604
name:-0.02183985710144
name:-0.0029079914093018
Normoyle; Kevin Patent Filings

Normoyle; Kevin

Patent Applications and Registrations

Patent applications and USPTO patent grants for Normoyle; Kevin.The latest application filed is for "memory pools in a memory model for a unified computing system".

Company Profile
2.26.18
  • Normoyle; Kevin - Los Gatos CA
  • Normoyle; Kevin - Big Pine CA
  • NORMOYLE; Kevin - Los Altos CA
  • Normoyle; Kevin - Santa Clara CA
  • Normoyle; Kevin - San Jose CA
  • Normoyle; Kevin - Mountain View CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Memory Pools In A Memory Model For A Unified Computing System
App 20210406196 - Asaro; Anthony ;   et al.
2021-12-30
Memory pools in a memory model for a unified computing system
Grant 11,119,944 - Asaro , et al. September 14, 2
2021-09-14
Memory Pools In A Memory Model For A Unified Computing System
App 20190303302 - Asaro; Anthony ;   et al.
2019-10-03
Memory heaps in a memory model for a unified computing system
Grant 10,324,860 - Asaro , et al.
2019-06-18
Managing coherent memory between an accelerated processing device and a central processing unit
Grant 9,965,392 - Asaro , et al. May 8, 2
2018-05-08
Memory Heaps In A Memory Model For A Unified Computing System
App 20180011798 - ASARO; Anthony ;   et al.
2018-01-11
Memory Heaps In A Memory Model For A Unified Computing System
App 20160371197 - ASARO; Anthony ;   et al.
2016-12-22
Managing Coherent Memory Between An Accelerated Processing Device And A Central Processing Unit
App 20160364334 - Asaro; Anthony ;   et al.
2016-12-15
Memory heaps in a memory model for a unified computing system
Grant 9,448,930 - Asaro , et al. September 20, 2
2016-09-20
Managing coherent memory between an accelerated processing device and a central processing unit
Grant 9,430,391 - Asaro , et al. August 30, 2
2016-08-30
Memory Heaps In A Memory Model For A Unified Computing System
App 20150363310 - ASARO; Anthony ;   et al.
2015-12-17
Memory heaps in a memory model for a unified computing system
Grant 9,116,809 - Asaro , et al. August 25, 2
2015-08-25
Shared memory space in a unified memory model
Grant 9,009,419 - Asaro , et al. April 14, 2
2015-04-14
Visibility ordering in a memory model for a unified computing system
Grant 8,984,511 - Asaro , et al. March 17, 2
2015-03-17
Cache management for memory operations
Grant 8,935,475 - Asaro , et al. January 13, 2
2015-01-13
Shared Memory Space in a Unified Memory Model
App 20140040565 - ASARO; Anthony ;   et al.
2014-02-06
Memory Heaps in a Memory Model for a Unified Computing System
App 20130262784 - Asaro; Anthony ;   et al.
2013-10-03
Managing Coherent Memory Between an Accelerated Processing Device and a Central Processing Unit
App 20130262776 - ASARO; Anthony ;   et al.
2013-10-03
Mapping Memory Instructions into a Shared Memory Address Place
App 20130262814 - Asaro; Anthony ;   et al.
2013-10-03
Cache Management for Memory Operations
App 20130262775 - ASARO; Anthony ;   et al.
2013-10-03
Visibility Ordering in a Memory Model for a Unified Computing System
App 20130263141 - Asaro; Anthony ;   et al.
2013-10-03
Ordering operation
Grant 7,552,302 - Tene , et al. June 23, 2
2009-06-23
Speculative multiaddress atomicity
Grant 7,376,800 - Choquette , et al. May 20, 2
2008-05-20
Method and apparatus for enhancing the speed of a synchronous bus
Grant 7,143,304 - Raghava , et al. November 28, 2
2006-11-28
Method and apparatus for enhancing the speed of a synchronous bus
App 20040243876 - Raghava, Sharath ;   et al.
2004-12-02
Method and apparatus for dynamically switching a cache between direct-mapped and 4-way set associativity
Grant 6,446,168 - Normoyle , et al. September 3, 2
2002-09-03
Transaction activation processor for controlling memory transaction processing in a packet switched cache coherent multiprocessor system
Grant 5,905,998 - Ebrahim , et al. May 18, 1
1999-05-18
Multiple bus bridge system for maintaining a complete order by delaying servicing interrupts while posting write requests
Grant 5,894,587 - Normoyle , et al. April 13, 1
1999-04-13
System level mechanism for invalidating data stored in the external cache of a processor in a computer system
Grant 5,737,755 - Ebrahim , et al. April 7, 1
1998-04-07
Cache coherent computer system that minimizes invalidation and copyback operations
Grant 5,706,463 - Ebrahim , et al. January 6, 1
1998-01-06
Writeback cancellation processing system for use in a packet switched cache coherent multiprocessor system
Grant 5,684,977 - Van Loo , et al. November 4, 1
1997-11-04
Memory transaction execution system and method for multiprocessor system having independent parallel transaction queues associated with each processor
Grant 5,657,472 - Van Loo , et al. August 12, 1
1997-08-12
Transaction activation processor for controlling memory transaction execution in a packet switched cache coherent multiprocessor system
Grant 5,655,100 - Ebrahim , et al. August 5, 1
1997-08-05
Fast, dual ported cache controller for data processors in a packet switched cache coherent multiprocessor system
Grant 5,644,753 - Ebrahim , et al. July 1, 1
1997-07-01
Packet switched cache coherent multiprocessor system
Grant 5,634,068 - Nishtala , et al. May 27, 1
1997-05-27

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