Noble; Ross E.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Noble; Ross E..The latest application filed is for "method for forming a through silicon via (tsv)".

Company Profile

0.5.7

Noble; Ross E. - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Dual interlayer dielectric stressor integration with a sacrificial underlayer film stack Grant 8,247,850 - Jawarani , et al. August 21, 2	2012-08-21
Method for forming a through silicon via (TSV) Grant 8,039,386 - Dao , et al. October 18, 2	2011-10-18
Method For Forming A Through Silicon Via (tsv) App 20110237073 - Dao; Thuy B. ; et al.	2011-09-29
Method of forming a semiconductor layer Grant 7,972,922 - Martinez , et al. July 5, 2	2011-07-05
Method Of Forming A Semiconductor Layer App 20100129952 - Martinez; Hunter J. ; et al.	2010-05-27
Method to control uniformity/composition of metal electrodes, silicides on topography and devices using this method Grant 7,611,936 - Mathew , et al. November 3, 2	2009-11-03
Method to control uniformity/composition of metal electrodes, silicides on topography and devices using this method App 20080280429 - Mathew; Leo ; et al.	2008-11-13
Dual interlayer dielectric stressor integration with a sacrificial underlayer film stack App 20080164531 - Jawarani; Dharmesh ; et al.	2008-07-10
Removing Metal Using An Oxidizing Chemistry App 20070295357 - Lovejoy; Michael Luke ; et al.	2007-12-27
Semiconductor fabrication process including source/drain recessing and filling App 20060115949 - Zhang; Da ; et al.	2006-06-01
Semiconductor device having an insulating layer and method for forming Grant 6,908,822 - Rendon , et al. June 21, 2	2005-06-21
Semiconductor device having an insulating layer and method for forming App 20050056899 - Rendon, Michael J. ; et al.	2005-03-17

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