Nishikawa; Hiroo
Patent Applications and Registrations
Patent applications and USPTO patent grants for Nishikawa; Hiroo.The latest application filed is for "apparatus for reducing the latency of sum-addressed shifters".
- Nishikawa; Hiroo - Shiga JP
- Nishikawa, Hiroo - Kusatsu-shi JP
| Patent | Date |
|---|---|
| Reducing the latency of sum-addressed shifters Grant 8,166,085 - Dhong , et al. April 24, 2 | 2012-04-24 |
| Methods and apparatus for performing multi-value range checks Grant 7,469,265 - Dhong , et al. December 23, 2 | 2008-12-23 |
| Apparatus for Reducing the Latency of Sum-Addressed Shifters App 20080195684 - Dhong; Sang Hoo ; et al. | 2008-08-14 |
| Apparatus and method for reducing the latency of sum-addressed shifters Grant 7,392,270 - Dhong , et al. June 24, 2 | 2008-06-24 |
| Apparatus and method for reducing the latency of sum-addressed shifters App 20060026223 - Dhong; Sang Hoo ; et al. | 2006-02-02 |
| Fast operand formatting for a high performance multiply-add floating point-unit App 20050228844 - Dhong, Sang H. ; et al. | 2005-10-13 |
| Methods and apparatus for performing multi-value range checks App 20050086279 - Dhong, Sang Hoo ; et al. | 2005-04-21 |
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