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Lockstepped CPU selection based on failure status
Grant 10,365,979 - Nishii , et al. July 30, 2 | 2019-07-30 |
Semiconductor Device
App 20170308445 - NISHII; Osamu ; et al. | 2017-10-26 |
Semiconductor device with output data selection of lockstepped computing elements based on diagnostic information
Grant 9,734,023 - Nishii , et al. August 15, 2 | 2017-08-15 |
Semiconductor Device
App 20160034368 - Nishii; Osamu ; et al. | 2016-02-04 |
Substrate bias switching unit for a low power processor
Grant 8,364,988 - Totsuka , et al. January 29, 2 | 2013-01-29 |
Processor system using synchronous dynamic memory
Grant 8,234,441 - Uchiyama , et al. July 31, 2 | 2012-07-31 |
Data processing system with branch target addressing using upper and lower bit permutation
Grant 8,145,889 - Nishii March 27, 2 | 2012-03-27 |
Processor System Using Synchronous Dynamic Memory
App 20110314213 - UCHIYAMA; Kunio ; et al. | 2011-12-22 |
Substrate Bias Switching Unit For A Low Power Processor
App 20110208983 - TOTSUKA; Yonetaro ; et al. | 2011-08-25 |
Substrate bias switching unit for a low power processor
Grant 7,958,379 - Totsuka , et al. June 7, 2 | 2011-06-07 |
Processor system using synchronous dynamic memory
Grant 7,904,641 - Uchiyama , et al. March 8, 2 | 2011-03-08 |
Data Processing System
App 20110040954 - NISHII; OSAMU | 2011-02-17 |
Data processing system to calculate indexes into a branch target address table based on a current operating mode
Grant 7,836,286 - Nishii November 16, 2 | 2010-11-16 |
Memory system performing fast access to a memory location by omitting the transfer of a redundant address
Grant RE41,589 - Nishii , et al. August 24, 2 | 2010-08-24 |
Substrate Bias Switching Unit For A Low Power Processor
App 20100005324 - TOTSUKA; Yonetaro ; et al. | 2010-01-07 |
Substrate bias switching unit for a low power processor
Grant 7,475,261 - Totsuka , et al. January 6, 2 | 2009-01-06 |
Processor System Using Synchronous Dynamic Memory
App 20080229004 - UCHIYAMA; Kunio ; et al. | 2008-09-18 |
Data Processing System
App 20080201562 - NISHII; Osamu | 2008-08-21 |
Processor system using synchronous dynamic memory
Grant 7,376,783 - Uchiyama , et al. May 20, 2 | 2008-05-20 |
Semiconductor device
App 20080016383 - Watanabe; Takao ; et al. | 2008-01-17 |
Semiconductor device
Grant 7,254,082 - Watanabe , et al. August 7, 2 | 2007-08-07 |
Processor system using synchronous dynamic memory
App 20070061537 - Uchiyama; Kunio ; et al. | 2007-03-15 |
Halting clock signals to input and result latches in processing path upon fetching of instruction not supported
Grant 7,178,046 - Yamada , et al. February 13, 2 | 2007-02-13 |
Processor system using synchronous dynamic memory
Grant 7,143,230 - Uchiyama , et al. November 28, 2 | 2006-11-28 |
Semiconductor device
App 20060146635 - Watanabe; Takao ; et al. | 2006-07-06 |
Semiconductor device
Grant 7,023,757 - Watanabe , et al. April 4, 2 | 2006-04-04 |
Program counter (PC) relative addressing mode with fast displacement
Grant 7,003,651 - Kondoh , et al. February 21, 2 | 2006-02-21 |
Low power consumption microprocessor
App 20050169086 - Yamada, Tetsuya ; et al. | 2005-08-04 |
Semiconductor integrated circuit device
Grant 6,879,188 - Miyazaki , et al. April 12, 2 | 2005-04-12 |
Substituting specified instruction with NOP to functional unit and halting clock pulses to data latches for power saving
Grant 6,877,087 - Yamada , et al. April 5, 2 | 2005-04-05 |
Low power processor
App 20040158756 - Totsuka, Yonetaro ; et al. | 2004-08-12 |
Processor system using synchronous dynamic memory
App 20040143700 - Uchiyama, Kunio ; et al. | 2004-07-22 |
Processor for controlling substrate biases in accordance to the operation modes of the processor
Grant 6,715,090 - Totsuka , et al. March 30, 2 | 2004-03-30 |
Processor system using synchronous dynamic memory
Grant 6,697,908 - Uchiyama , et al. February 24, 2 | 2004-02-24 |
Semiconductor device
App 20030231526 - Watanabe, Takao ; et al. | 2003-12-18 |
Arithmetic apparatus for performing high speed multiplication and addition operations
App 20030233384 - Nishii, Osamu | 2003-12-18 |
System LSI having a substrate-bias generation circuit with a substrate-bias control-value storage unit
Grant 6,654,305 - Tsunoda , et al. November 25, 2 | 2003-11-25 |
Low power processor
Grant 6,604,202 - Nishii , et al. August 5, 2 | 2003-08-05 |
Semiconductor integrated circuit device
App 20030098730 - Miyazaki, Masayuki ; et al. | 2003-05-29 |
Data processor
App 20030063513 - Tsunoda, Takanobu ; et al. | 2003-04-03 |
Semiconductor integrated circuit device
Grant 6,515,519 - Miyazaki , et al. February 4, 2 | 2003-02-04 |
Program counter (PC) relative addressing mode with fast displacement
App 20020108029 - Kondoh, Yuki ; et al. | 2002-08-08 |
Semiconductor integrated circuit device and information processing device employing semiconductor integrated circuit device
App 20020064066 - Nishii, Osamu ; et al. | 2002-05-30 |
Processor system using synchronous dynamic memory
App 20020029317 - Uchiyama, Kunio ; et al. | 2002-03-07 |
Semiconductor integrated circuit device and information processing device employing semiconductor integrated circuit device
App 20020003719 - Nishii, Osamu ; et al. | 2002-01-10 |
Data processor and data processing system having two translation lookaside buffers
Grant 6,092,172 - Nishimoto , et al. July 18, 2 | 2000-07-18 |
Data processor and data processing system
Grant 5,918,045 - Nishii , et al. June 29, 1 | 1999-06-29 |
Multiprocessor system having a processor invalidating operand cache when lock-accessing
Grant 5,740,401 - Hanawa , et al. April 14, 1 | 1998-04-14 |
Processor system using synchronous dynamic memory
Grant 5,574,876 - Uchiyama , et al. November 12, 1 | 1996-11-12 |
Integrated circuit data processor including a control pin for deactivating the driving of a data bus without deactivating that of an address bus
Grant 5,557,760 - Nishii , et al. September 17, 1 | 1996-09-17 |
Multiprocessor system having shared memory divided into a plurality of banks with access queues corresponding to each bank
Grant 5,375,215 - Hanawa , et al. December 20, 1 | 1994-12-20 |
Data processor having two instruction registers connected in cascade and two instruction decoders
Grant 5,301,285 - Hanawa , et al. April 5, 1 | 1994-04-05 |
Multi-processor system for invalidating hierarchical cache
Grant 5,287,484 - Nishii , et al. February 15, 1 | 1994-02-15 |
Multiprocessor cache system having three states for generating invalidating signals upon write accesses
Grant 5,283,886 - Nishii , et al. February 1, 1 | 1994-02-01 |
Static memory containing sense amp and sense amp switching circuit
Grant 5,267,198 - Hatano , et al. November 30, 1 | 1993-11-30 |
Static memory containing sense AMP and sense AMP switching circuit
Grant 5,193,075 - Hatano , et al. March 9, 1 | 1993-03-09 |
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