Ning; Xian J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ning; Xian J..The latest application filed is for "bond pad for low k dielectric materials and method for manufacture for semiconductor devices".

Company Profile

0.36.33

Ning; Xian J. - Shanghai N/A CN
Ning; Xian J - Shanghai CN
Ning; Xian J. - Mohegan Lake NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Bond pad for low K dielectric materials and method for manufacture for semiconductor devices Grant 8,395,240 - Ning March 12, 2	2013-03-12
Method for circuit layout and rapid thermal annealing method for semiconductor apparatus Grant 8,392,863 - Ju , et al. March 5, 2	2013-03-05
Method of forming a via structure dual damascene structure for the manufacture of semiconductor integrated circuit devices Grant 8,158,520 - Ning April 17, 2	2012-04-17
Bond Pad For Low K Dielectric Materials And Method For Manufacture For Semiconductor Devices App 20120034771 - NING; XIAN J.	2012-02-09
Method and structure using a pure silicon dioxide hardmask for gate patterning for strained silicon MOS transistors Grant 8,106,423 - Wu , et al. January 31, 2	2012-01-31
Bond pad for low K dielectric materials and method for manufacture for semiconductor devices Grant 8,049,308 - Ning November 1, 2	2011-11-01
Design Method for Circuit Layout and Rapid Thermal Annealing Method for Semiconductor Apparatus App 20110078647 - Ju; Jianhua ; et al.	2011-03-31
Single mask scheme method and structure for integrating PMOS and NMOS transistors using strained silicon Grant 7,820,500 - Ning October 26, 2	2010-10-26
Metal hard mask method and structure for strained silicon MOS transistors Grant 7,709,336 - Ning , et al. May 4, 2	2010-05-04
Seal ring corner design Grant 7,663,159 - Ning February 16, 2	2010-02-16
Dummy patterns and method of manufacture for mechanical strength of low K dielectric materials in copper interconnect structures for semiconductor devices Grant 7,605,470 - Ning October 20, 2	2009-10-20
Method and structure for second spacer formation for strained silicon MOS transistors Grant 7,591,659 - Chen , et al. September 22, 2	2009-09-22
Integration scheme method and structure for transistors using strained silicon Grant 7,547,595 - Ning June 16, 2	2009-06-16
Method and structure using a pure silicon dioxide hardmask for gate pattering for strained silicon MOS transistors App 20090065805 - Wu; Hanming ; et al.	2009-03-12
Seal ring structures with unlanded via stacks Grant 7,479,699 - Ning January 20, 2	2009-01-20
Method and structure using a pure silicon dioxide hardmask for gate patterning for strained silicon MOS transistors Grant 7,425,488 - Wu , et al. September 16, 2	2008-09-16
Dummy Patterns And Method Of Manufacture For Mechanical Strength Of Low K Dielectric Materials In Copper Interconnect Structures For Semiconductor Devices App 20080142975 - Ning; Xian J.	2008-06-19
Polysilicon gate doping method and structure for strained silicon MOS transistors Grant 7,335,566 - Ning , et al. February 26, 2	2008-02-26
Poly Silicon Gate Doping Method and Structure for Strained Silicon MOS Transistors App 20070184668 - Ning; Xian J. ; et al.	2007-08-09
Seal Ring Structures With Unlanded Via Stacks App 20070145567 - NING; XIAN J.	2007-06-28
Bond pad for low K dielectric materials and method for manufacture for semiconductor devices App 20070122597 - Ning; Xian J.	2007-05-31
Integration scheme method and structure for transistors using strained silicon App 20070099369 - Ning; Xian J.	2007-05-03
Single mask scheme method and structure for integrating PMOS and NMOS transistors using strained silicon App 20070096201 - Ning; Xian J.	2007-05-03
Method and structure for second spacer formation for strained silicon MOS transistors App 20070077716 - Chen; John ; et al.	2007-04-05
Seal ring corner design App 20070069336 - Ning; Xian J.	2007-03-29
Method and structure using a pure silicon dioxide hardmask for gate patterning for strained silicon MOS transistors App 20070063221 - Wu; Hanming ; et al.	2007-03-22
Metal hard mask method and structure for strained silicon MOS transistors App 20060194395 - Ning; Xian J. ; et al.	2006-08-31
Method and structure for reducing contact resistance in dual damascene structure for the manufacture of semiconductor devices App 20060060971 - Ning; Xian J.	2006-03-23
Lithography alignment and overlay measurement marks formed by resist mask blocking for MRAMs Grant 6,979,526 - Ning December 27, 2	2005-12-27
Vertical MIMCap manufacturing method Grant 6,960,365 - Ning November 1, 2	2005-11-01
MRAM MTJ stack to conductive line alignment method Grant 6,858,441 - Nuetzel , et al. February 22, 2	2005-02-22
Material combinations for tunnel junction cap layer, tunnel junction hard mask and tunnel junction stack seed layer in MRAM processing Grant 6,815,248 - Leuschner , et al. November 9, 2	2004-11-09
MIM capacitor structures and fabrication methods in dual-damascene structures Grant 6,794,262 - Ning , et al. September 21, 2	2004-09-21
Design of lithography alignment and overlay measurement marks on CMP finished damascene surface Grant 6,780,775 - Ning August 24, 2	2004-08-24
Method for generating alignment marks for manufacturing MIM capacitors Grant 6,750,115 - Ning , et al. June 15, 2	2004-06-15
Method For Generating Alignment Marks For Manufacturing Mim Capacitors App 20040102014 - Ning, Xian J. ; et al.	2004-05-27
Method for making a metal-insulator-metal capacitor using plate-through mask techniques Grant 6,723,600 - Wong , et al. April 20, 2	2004-04-20
Single RIE process for MIMcap top and bottom plates Grant 6,713,395 - Ning March 30, 2	2004-03-30
MIM capacitor structures and fabrication methods in dual-damascene structures App 20040056324 - Ning, Xian J. ; et al.	2004-03-25
Method of manufacturing a metal cap layer for preventing damascene conductive lines from oxidation Grant 6,709,874 - Ning March 23, 2	2004-03-23
Method of fabricating an integrated circuit having embedded vertical capacitor Grant 6,706,588 - Ning March 16, 2	2004-03-16
MRAM MTJ stack to conductive line alignment method App 20040043579 - Nuetzel, Joachim ; et al.	2004-03-04
Self-aligned conductive line for cross-point magnetic memory integrated circuits Grant 6,692,898 - Ning February 17, 2	2004-02-17
Stacked MIMCap between Cu dual damascene levels Grant 6,677,635 - Ning , et al. January 13, 2	2004-01-13
Lithography alignment and overlay measurement marks formed by resist mask blocking for MRAMs App 20030224260 - Ning, Xian J.	2003-12-04
Material combinations for tunnel junction cap layer, tunnel junction hard mask and tunnel junction stack seed layer in MRAM processing App 20030199104 - Leuschner, Rainer ; et al.	2003-10-23
Plate-through hard mask for MRAM devices Grant 6,635,496 - Ning October 21, 2	2003-10-21
Method of fabricating a metal-insulator-metal (MIM) capacitor Grant 6,620,701 - Ning September 16, 2	2003-09-16
Self-aligned cross-point MRAM device with aluminum metallization layers Grant 6,611,453 - Ning August 26, 2	2003-08-26
Vertical MIMCap manufacturing method App 20030143322 - Ning, Xian J.	2003-07-31
Stacked metal-insulator-metal capacitor structures in between interconnection layers App 20030113974 - Ning, Xian J. ; et al.	2003-06-19
Vertical/horizontal MIMCap method App 20030073282 - Ning, Xian J.	2003-04-17
Plate-through hard mask for MRAM devices App 20030073251 - Ning, Xian J.	2003-04-17
MIMCap with high dielectric constant insulator App 20030006480 - Lian, Jenny ; et al.	2003-01-09
Method of making stacked MIMCap between Cu dual-damascene levels App 20020182794 - Ning, Xian J. ; et al.	2002-12-05
Single rie process for mimcap top and bottom plates App 20020173159 - Ning, Xian J.	2002-11-21
Method for making a metal-insulator-metal capacitor using plate-through mask techniques App 20020153551 - Wong, Kwong H. ; et al.	2002-10-24
Self-aligned double-sided vertical MIMcap Grant 6,451,667 - Ning September 17, 2	2002-09-17
Self-aligned conductive line for cross-point magnetic memory integrated circuits App 20020098281 - Ning, Xian J.	2002-07-25
Design of lithography alignment and overlay measurement marks on CMP finished damascene surface App 20020098707 - Ning, Xian J.	2002-07-25
Self-aligned cross-point MRAM device with aluminum metallization layers App 20020097600 - Ning, Xian J.	2002-07-25
Metal Hard Mask For Ild Rie Processing Of Semiconductor Memory Devices To Prevent Oxidation Of Conductive Lines App 20020098676 - Ning, Xian J. ; et al.	2002-07-25
A method of manufacturing a metal cap layer for preventing damascene conductive lines from oxidation App 20020096775 - Ning, Xian J.	2002-07-25
Self-aligned double-sided vertical MIMcap App 20020081814 - Ning, Xian J.	2002-06-27
Dry process for cleaning residues/polymers after metal etch Grant 6,184,134 - Chaudhary , et al. February 6, 2	2001-02-06
Method for detecting under-etched vias Grant 5,903,343 - Ning , et al. May 11, 1	1999-05-11
Wafer surface cleaning apparatus and method Grant 5,865,901 - Yin , et al. February 2, 1	1999-02-02

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