Nikitin; Andrey A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Nikitin; Andrey A..The latest application filed is for "method and system for outputting a sequence of commands and data described by a flowchart".

Company Profile

0.22.20

Nikitin; Andrey A. - Moscow RU

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and system for outputting a sequence of commands and data described by a flowchart Grant 8,006,209 - Nikitin , et al. August 23, 2	2011-08-23
Digital Gaussian noise simulator Grant 7,822,099 - Nikitin , et al. October 26, 2	2010-10-26
Method and system for outputting a sequence of commands and data described by a flowchart App 20090094571 - Nikitin; Andrey A. ; et al.	2009-04-09
Method and system for outputting a sequence of commands and data described by a flowchart Grant 7,472,358 - Nikitin , et al. December 30, 2	2008-12-30
Method and system for outputting a sequence of commands and data described by a flowchart Grant 7,415,691 - Andreev , et al. August 19, 2	2008-08-19
Method and system for mapping netlist of integrated circuit to design Grant 7,404,166 - Andreev , et al. July 22, 2	2008-07-22
Method and system for converting netlist of integrated circuit between libraries Grant 7,380,223 - Panteleev , et al. May 27, 2	2008-05-27
Method for evaluating logic functions by logic circuits having optimized number of and/or switches Grant 7,328,423 - Nikitin , et al. February 5, 2	2008-02-05
Verification of RRAM tiling netlist Grant 7,315,993 - Nikitin , et al. January 1, 2	2008-01-01
Digital Gaussian Noise Simulator App 20070230621 - Nikitin; Andrey A. ; et al.	2007-10-04
Digital gaussian noise simulator Grant 7,263,470 - Nikitin , et al. August 28, 2	2007-08-28
Method for optimizing execution time of parallel processor programs Grant 7,257,807 - Nikitin , et al. August 14, 2	2007-08-14
Method and system for outputting a sequence of commands and data described by a flowchart App 20070169009 - Nikitin; Andrey A. ; et al.	2007-07-19
Process and apparatus for memory mapping Grant 7,219,321 - Nikitin , et al. May 15, 2	2007-05-15
Method and system for mapping netlist of integrated circuit to design App 20070094633 - Andreev; Alexander E. ; et al.	2007-04-26
Method and system for converting netlist of integrated circuit between libraries App 20070094621 - Panteleev; Pavel ; et al.	2007-04-26
Process and apparatus for placing cells in an IC floorplan Grant 7,210,113 - Andreev , et al. April 24, 2	2007-04-24
Yield driven memory placement system Grant 7,168,052 - Andreev , et al. January 23, 2	2007-01-23
Process and apparatus for fast assignment of objects to a rectangle Grant 7,111,264 - Andreev , et al. September 19, 2	2006-09-19
Optimizing depths of circuits for Boolean functions Grant 7,103,868 - Nikitin , et al. September 5, 2	2006-09-05
Method and apparatus of IC implementation based on C++ language description Grant 7,082,593 - Nikitin , et al. July 25, 2	2006-07-25
Verification of RRAM tiling netlist App 20060117281 - Nikitin; Andrey A. ; et al.	2006-06-01
Decision function generator for a Viterbi decoder Grant 7,039,855 - Nikitin , et al. May 2, 2	2006-05-02
Process and apparatus for placement of cells in an IC during floorplan creation Grant 7,036,102 - Andreev , et al. April 25, 2	2006-04-25
Method and system for outputting a sequence of commands and data described by a flowchart App 20060020927 - Andreev; Alexander E. ; et al.	2006-01-26
Yield driven memory placement system App 20060010092 - Andreev; Alexander E. ; et al.	2006-01-12
Process and apparatus for placing cells in an IC floorplan App 20050240889 - Andreev, Alexander E. ; et al.	2005-10-27
Process and apparatus for memory mapping App 20050240746 - Nikitin, Andrey A. ; et al.	2005-10-27
Method for evaluating logic functions by logic circuits having optimized number of and/or switches App 20050149302 - Nikitin, Andrey A. ; et al.	2005-07-07
Method for evaluating logic functions by logic circuits having optimized number of and/or switches Grant 6,901,573 - Nikitin , et al. May 31, 2	2005-05-31
Process and apparatus for placement of cells in an IC during floorplan creation App 20050091625 - Andreev, Alexander E. ; et al.	2005-04-28
Process and apparatus for fast assignment of objects to a rectangle App 20050086624 - Andreev, Alexander E. ; et al.	2005-04-21
Parallel processor language, method for translating C++ programs into this language, and method for optimizing execution time of parallel processor programs App 20050066321 - Nikitin, Andrey A. ; et al.	2005-03-24
Method and apparatus of IC implementation based on C++ language description App 20050013155 - Nikitin, Andrey A. ; et al.	2005-01-20
Digital gaussian noise simulator App 20040225481 - Nikitin, Andrey A. ; et al.	2004-11-11
Method for evaluating logic functions by logic circuits having optimized number of and/or switches App 20040177330 - Nikitin, Andrey A. ; et al.	2004-09-09
Decision function generator for a viterbi decoder App 20040153955 - Nikitin, Andrey A. ; et al.	2004-08-05
Optimizing depths of circuits for Boolean functions App 20040093578 - Nikitin, Andrey A. ; et al.	2004-05-13
Overlap remover manager Grant 6,701,503 - Nikitin , et al. March 2, 2	2004-03-02
Direct transformation of engineering change orders to synthesized IC chip designs Grant 6,651,239 - Nikitin , et al. November 18, 2	2003-11-18
Blocked net buffer insertion Grant 6,615,401 - Gasanov , et al. September 2, 2	2003-09-02
Overlap remover manager App 20030149952 - Nikitin, Andrey A. ; et al.	2003-08-07