Nierle; Klaus

Patent Applications and Registrations

Patent applications and USPTO patent grants for Nierle; Klaus.The latest application filed is for "apparatus and method for manufacturing a multiple-chip memory device".

Company Profile

0.10.13

Nierle; Klaus - Essex Junction VT US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Apparatus and method for manufacturing a multiple-chip memory device with multi-stage testing Grant 8,468,401 - Lee , et al. June 18, 2	2013-06-18
Apparatus and Method for Manufacturing a Multiple-Chip Memory Device App 20100306605 - Lee; KoonHee ; et al.	2010-12-02
System and method for addressing errors in a multiple-chip memory device Grant 7,802,133 - Lee , et al. September 21, 2	2010-09-21
Method and system for testing an integrated circuit Grant 7,729,186 - Kliewer , et al. June 1, 2	2010-06-01
System and method for addressing errors in a multiple-chip memory device App 20090006887 - Lee; KoonHee ; et al.	2009-01-01
Method and circuit for stressing upper level interconnects in semiconductor devices App 20080285358 - Nierle; Klaus	2008-11-20
Method and circuit for stressing upper level interconnects in semiconductor devices App 20080237587 - Nierle; Klaus ; et al.	2008-10-02
Method and System for Testing an Integrated Circuit App 20080205173 - Kliewer; Joerg ; et al.	2008-08-28
Method and apparatus for increasing clock frequency and data rate for semiconductor devices Grant 7,385,872 - Nierle , et al. June 10, 2	2008-06-10
Method And Apparatus For Increasing Clock Frequency And Data Rate For Semiconductor Devices App 20080089164 - Nierle; Klaus ; et al.	2008-04-17
Test mode method and apparatus for internal memory timing signals Grant 7,339,841 - Versen , et al. March 4, 2	2008-03-04
Serial presence detect functionality on memory component Grant 7,263,019 - Nierle , et al. August 28, 2	2007-08-28
Test mode method and apparatus for internal memory timing signals App 20070064505 - Versen; Martin ; et al.	2007-03-22
Serial presence detect functionality on memory component App 20070058470 - Nierle; Klaus ; et al.	2007-03-15
Testmode and test method for increased stress duty cycles during burn in App 20070038804 - Nierle; Klaus ; et al.	2007-02-15
Method for full wafer contact probing, wafer design and probe card device with reduced probe contacts Grant 7,157,923 - Schneider , et al. January 2, 2	2007-01-02
Method for testing the serviceability of bit lines in a DRAM memory device Grant 7,120,070 - Versen , et al. October 10, 2	2006-10-10
Method and device for varying an active duty cycle of a wordline Grant 7,072,234 - Nierle July 4, 2	2006-07-04
Test method, control circuit and system for reduced time combined write window and retention testing App 20060136791 - Nierle; Klaus	2006-06-22
Method for full wafer contact probing, wafer design and probe card device App 20060103401 - Schneider; Peter ; et al.	2006-05-18
Method for testing the serviceability of bit lines in a DRAM memory device App 20060048022 - Versen; Martin ; et al.	2006-03-02
Internal data generation and compare via unused external pins App 20040133827 - Norris, Alan D. ; et al.	2004-07-08

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