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Patent applications and USPTO patent grants for Niemic; Andrew.The latest application filed is for "test architecture having multiple fpga based hardware accelerator blocks for testing multiple duts independently".
Patent | Date |
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Tester with acceleration on memory and acceleration for automatic pattern generation within a FPGA block Grant 10,161,993 - Frediani , et al. Dec | 2018-12-25 |
Tester with mixed protocol engine in a FPGA block Grant 9,952,276 - Frediani , et al. April 24, 2 | 2018-04-24 |
Tester With Mixed Protocol Engine In A Fpga Block App 20140236526 - FREDIANI; JOHN ;   et al. | 2014-08-21 |
Test Architecture Having Multiple Fpga Based Hardware Accelerator Blocks For Testing Multiple Duts Independently App 20140236525 - CHAN; Gerald ;   et al. | 2014-08-21 |
Tester With Acceleration On Memory And Acceleration For Automatic Pattern Generation Within A Fpga Block App 20140236524 - FREDIANI; John ;   et al. | 2014-08-21 |
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