| Patent | Date |
|---|
Symmetric multiprocessing system with unified environment and distributed system functions wherein bus operations related storage spaces are mapped into a single system address space
Grant 6,125,436 - Bertone , et al. September 26, 2 | 2000-09-26 |
Symmetric multiprocessing system with unified environment and distributed system functions
Grant 5,956,522 - Bertone , et al. September 21, 1 | 1999-09-21 |
Adaptively generating timing signals for access to various memory devices based on stored profiles
Grant 5,809,340 - Bertone , et al. September 15, 1 | 1998-09-15 |
Symmetric multiprocessing system with unified environment and distributed system functions
Grant 5,522,069 - Bertone , et al. May 28, 1 | 1996-05-28 |
Symmetric multiprocessing system with unified environment and distributed system functions
Grant 5,517,648 - Bertone , et al. May 14, 1 | 1996-05-14 |
High speed burst read address generation with high speed transfer
Grant 5,345,573 - Bowden, III , et al. September 6, 1 | 1994-09-06 |
High performance burst read data transfer operation
Grant 5,291,580 - Bowden, III , et al. March 1, 1 | 1994-03-01 |
Apparatus for loading and verifying a control store memory of a central subsystem
Grant 4,910,666 - Nibby, Jr. , et al. March 20, 1 | 1990-03-20 |
Cache resiliency in processing a variety of address faults
Grant 4,833,601 - Barlow , et al. May 23, 1 | 1989-05-23 |
Address transform method and apparatus for transferring addresses
Grant 4,799,222 - Barlow , et al. January 17, 1 | 1989-01-17 |
Pause apparatus for a memory controller with interleaved queuing apparatus
Grant 4,558,429 - Barlow , et al. December 10, 1 | 1985-12-10 |
Memory identification apparatus and method
Grant 4,545,010 - Salas , et al. October 1, 1 | 1985-10-01 |
Remap method and apparatus for a memory system which uses partially good memory devices
Grant 4,527,251 - Nibby, Jr. , et al. July 2, 1 | 1985-07-02 |
Partial defective chip memory support system
Grant 4,523,313 - Nibby, Jr. , et al. June 11, 1 | 1985-06-11 |
Memory system with automatic memory configuration
Grant 4,507,730 - Johnson , et al. March 26, 1 | 1985-03-26 |
Memory controller with interleaved queuing apparatus
Grant 4,451,880 - Johnson , et al. May 29, 1 | 1984-05-29 |
Sequential word aligned addressing apparatus
Grant 4,432,055 - Salas , et al. February 14, 1 | 1984-02-14 |
Apparatus for deferring error detection of multibyte parity encoded data received from a plurality of input/output data sources
Grant 4,388,684 - Nibby, Jr. , et al. June 14, 1 | 1983-06-14 |
Sequential word aligned address apparatus
Grant 4,376,972 - Johnson , et al. March 15, 1 | 1983-03-15 |
Memory controller with address independent burst mode capability
Grant 4,370,712 - Johnson , et al. January 25, 1 | 1983-01-25 |
Soft error rewrite control system
Grant 4,369,510 - Johnson , et al. January 18, 1 | 1983-01-18 |
Memory controller with burst mode capability
Grant 4,366,539 - Johnson , et al. December 28, 1 | 1982-12-28 |
Multimode memory system using a multiword common bus for double word and single word transfer
Grant 4,361,869 - Johnson , et al. November 30, 1 | 1982-11-30 |
Method and apparatus for testing and verifying the operation of error control apparatus within a memory
Grant 4,359,771 - Johnson , et al. November 16, 1 | 1982-11-16 |
Sequential chip select decode apparatus and method
Grant 4,323,965 - Johnson , et al. April 6, 1 | 1982-04-06 |
Double word fetch system
Grant 4,319,324 - Johnson , et al. March 9, 1 | 1982-03-09 |
Data processing system having centralized memory refresh
Grant 4,317,169 - Panepinto, Jr. , et al. February 23, 1 | 1982-02-23 |
Memory present apparatus
Grant 4,303,993 - Panepinto, Jr. , et al. December 1, 1 | 1981-12-01 |
Rotating chip selection technique and apparatus
Grant 4,296,467 - Nibby, Jr. , et al. October 20, 1 | 1981-10-20 |
System providing multiple fetch bus cycle operation
Grant 4,236,203 - Curley , et al. November 25, 1 | 1980-11-25 |
Dynamic memory system which includes apparatus for performing refresh operations in parallel with normal memory operations
Grant 4,185,323 - Johnson , et al. January 22, 1 | 1980-01-22 |
Error detection and correction locator circuits
Grant 4,077,565 - Nibby, Jr. , et al. March 7, 1 | 1978-03-07 |
Apparatus and method for storing parity encoded data from a plurality of input/output sources
Grant 4,072,853 - Barlow , et al. February 7, 1 | 1978-02-07 |
Apparatus and method for generating timing signals for latched type memories
Grant 4,060,794 - Feldman , et al. November 29, 1 | 1977-11-29 |
Power strobing to achieve a tri state
Grant 4,044,330 - Johnson , et al. August 23, 1 | 1977-08-23 |
Apparatus And Method For Memory Refreshment Control
Grant 3,760,379 - Nibby, Jr. , et al. September 18, 1 | 1973-09-18 |
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