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Ni; Cheng-Tsung Patent Filings

Ni; Cheng-Tsung

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ni; Cheng-Tsung.The latest application filed is for "power metal oxide semiconductor field effect transistor layout".

Company Profile
0.6.4
  • Ni; Cheng-Tsung - Hsinchu TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Power metal oxide semiconductor field effect transistor layout
Grant 6,888,197 - Ni , et al. May 3, 2
2005-05-03
Method for forming dual oxide layers at bottom of trench
Grant 6,821,913 - Chuang , et al. November 23, 2
2004-11-23
Method of simultaneously implementing differential gate oxide thickness using fluorine bearing impurities
Grant 6,784,115 - Ni , et al. August 31, 2
2004-08-31
Power metal oxide semiconductor field effect transistor layout
App 20040113205 - Ni, Cheng-Tsung ;   et al.
2004-06-17
Fabricating a DMOS transistor
Grant 6,660,592 - Chuang , et al. December 9, 2
2003-12-09
MOS transistors having dual gates and self-aligned interconnect contact windows
Grant 6,657,263 - Ni December 2, 2
2003-12-02
Fabricating a DMOS transistor
App 20030096485 - Chuang, Chiao-Shun ;   et al.
2003-05-22
Method for forming dual oxide layers at bottom of trench
App 20030068901 - Chuang, Chiao-Shun ;   et al.
2003-04-10
MOS transistors having dual gates and self-aligned interconnect contact windows
App 20010049165 - Ni, Cheng-Tsung
2001-12-06
Method for fabricating MOSFET having increased effective gate length
Grant 6,127,699 - Ni , et al. October 3, 2
2000-10-03

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