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name:-0.014832973480225
name:-0.01124095916748
name:-0.00048303604125977
Nguyen; Phung T. Patent Filings

Nguyen; Phung T.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Nguyen; Phung T..The latest application filed is for "bipolar transistor integrated with metal gate cmos devices".

Company Profile
0.11.11
  • Nguyen; Phung T. - Pleasant Valley NY US
  • Nguyen; Phung T. - Hopewell Junction NY
  • Nguyen; Phung T. - Mission Viejo CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Bipolar transistor integrated with metal gate CMOS devices
Grant 8,569,840 - Wallner , et al. October 29, 2
2013-10-29
Bipolar Transistor Integrated With Metal Gate Cmos Devices
App 20120139056 - Wallner; Thomas A. ;   et al.
2012-06-07
Method of forming bipolar transistor integrated with metal gate CMOS devices
Grant 8,129,234 - Wallner , et al. March 6, 2
2012-03-06
One-transistor static random access memory with integrated vertical PNPN device
Grant 8,035,126 - Nguyen , et al. October 11, 2
2011-10-11
Bipolar Transistor Integrated With Metal Gate Cmos Devices
App 20110057266 - Wallner; Thomas A. ;   et al.
2011-03-10
Across reticle variation modeling and related reticle
Grant 7,803,644 - Balch , et al. September 28, 2
2010-09-28
One-transistor static random access memory with integrated vertical PNPN device
Grant 7,781,797 - Nguyen , et al. August 24, 2
2010-08-24
One-transistor Static Random Access Memory With Integrated Vertical Pnpn Device
App 20090108287 - Nguyen; Phung T. ;   et al.
2009-04-30
Across Reticle Variation Modeling And Related Reticle
App 20090068772 - Balch; Bruce W. ;   et al.
2009-03-12
One-transistor Static Random Access Memory With Integrated Vertical Pnpn Device
App 20080029781 - Nguyen; Phung T. ;   et al.
2008-02-07
Semiconductor Structure Including Isolation Region With Variable Linewidth And Method For Fabrication Therof
App 20070293016 - Luo; Zhijiong ;   et al.
2007-12-20
Buried well for semiconductor devices
App 20070069309 - Lindsay; Richard ;   et al.
2007-03-29
Structure for measurement of capacitance of ultra-thin dielectrics
Grant 6,980,009 - Maciejewski , et al. December 27, 2
2005-12-27
Structure For Measurement Of Capacitance Of Ultra-thin Dielectrics
App 20050088186 - Maciejewski, Edward P. ;   et al.
2005-04-28
SRAM cell with well contacts and P+ diffusion crossing to ground or N+ diffusion crossing to VDD
Grant 6,856,031 - Nguyen , et al. February 15, 2
2005-02-15
Method for low topography semiconductor device formation
Grant 6,797,569 - Colavito , et al. September 28, 2
2004-09-28
Method for low topography semiconductor device formation
Grant 6,624,486 - Colavito , et al. September 23, 2
2003-09-23
Method For Low Topography Semiconductor Device Formation
App 20030170941 - Colavito, David B. ;   et al.
2003-09-11
Method for low topography semiconductor device formation
App 20020175369 - Colavito, David B. ;   et al.
2002-11-28
Charger coupling
Grant 6,373,221 - Koike , et al. April 16, 2
2002-04-16
Charger coupling
App 20010035734 - Koike, Yasuhiro ;   et al.
2001-11-01

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