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Safety integrity level of service (SILoS) system
Grant 11,063,701 - Fruehling , et al. July 13, 2 | 2021-07-13 |
SAFETY INTEGRITY LEVEL OF SERVICE (SILoS) SYSTEM
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System and method for handling load and/or store operations in a superscalar microprocessor
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High-performance superscalar-based computer system with out-of order instruction execution and concurrent results distribution
Grant 7,941,635 - Nguyen , et al. May 10, 2 | 2011-05-10 |
RISC microprocessor architecture implementing multiple typed register sets
Grant 7,941,636 - Garg , et al. May 10, 2 | 2011-05-10 |
Superscalar RISC instruction scheduling
Grant 7,802,074 - Garg , et al. September 21, 2 | 2010-09-21 |
High-performance, superscalar-based computer system with out-of-order instruction execution
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High-performance, superscalar-based computer system with out-of-order instruction execution
Grant 7,721,070 - Nguyen , et al. May 18, 2 | 2010-05-18 |
RISC Microprocessor Architecture Implementing Multiple Typed Register Sets
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RISC microprocessor architecture implementing multiple typed register sets
Grant 7,685,402 - Garg , et al. March 23, 2 | 2010-03-23 |
System and method for translating non-native instructions to native instructions for processing on a host processor
Grant 7,664,935 - Coon , et al. February 16, 2 | 2010-02-16 |
Microprocessor architecture capable of supporting multiple heterogeneous processors
Grant 7,657,712 - Lentz , et al. February 2, 2 | 2010-02-02 |
High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution
Grant 7,555,632 - Nguyen , et al. June 30, 2 | 2009-06-30 |
Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip
Grant 7,555,738 - Iadonato , et al. June 30, 2 | 2009-06-30 |
RISC microprocessor architecture implementing multiple typed register sets
Grant 7,555,631 - Garg , et al. June 30, 2 | 2009-06-30 |
High-performance, superscalar-based computer system with out-of-order instruction execution
Grant 7,487,333 - Nguyen , et al. February 3, 2 | 2009-02-03 |
High-Performance, Superscalar-Based Computer System with Out-of-Order Instruction Execution
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System and Method for Translating Non-Native Instructions to Native Instructions for Processing on a Host Processor
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System and method for translating non-native instructions to native instructions for processing on a host processor
Grant 7,343,473 - Coon , et al. March 11, 2 | 2008-03-11 |
Superscalar RISC instruction scheduling
App 20080059770 - Garg; Sanjiv ; et al. | 2008-03-06 |
Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip
App 20070113214 - Iadonato; Kevin R. ; et al. | 2007-05-17 |
RISC microprocessor architecture implementing multiple typed register sets
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High-performance, superscalar-based computer system with out-of-order instruction execution
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High-performance superscalar-based computer system with out-of order instruction execution and concurrent results distribution
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Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip
Grant 7,174,525 - Iadonato , et al. February 6, 2 | 2007-02-06 |
High-performance, superscalar-based computer system with out-of-order instruction execution
Grant 7,162,610 - Nguyen , et al. January 9, 2 | 2007-01-09 |
High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution
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Superscalar RISC instruction scheduling
Grant 7,051,187 - Garg , et al. May 23, 2 | 2006-05-23 |
High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution
Grant 7,028,161 - Nguyen , et al. April 11, 2 | 2006-04-11 |
Microprocessor architecture capable of supporting multiple heterogeneous processors
App 20060064569 - Lentz; Derek J. ; et al. | 2006-03-23 |
Superscalar RISC instruction scheduling
App 20060041736 - Garg; Sanjiv ; et al. | 2006-02-23 |
High-performance, superscalar-based computer system with out-of-order instruction execution
Grant 6,986,024 - Nguyen , et al. January 10, 2 | 2006-01-10 |
System and method for handling load and/or store operations in a superscalar microprocessor
App 20050283591 - Brashears, Cheryl Senter ; et al. | 2005-12-22 |
System and method for handling load and/or store operations in a superscalar microprocessor
Grant 6,965,987 - Senter Brashears , et al. November 15, 2 | 2005-11-15 |
System and method for translating non-native instructions to native instructions for processing on a host processor
App 20050251653 - Coon, Brett ; et al. | 2005-11-10 |
High-performance, superscalar-based computer system with out-of-order instruction execution
Grant 6,959,375 - Nguyen , et al. October 25, 2 | 2005-10-25 |
System and method for translating non-native instructions to native instructions for processing on a host processor
Grant 6,954,847 - Coon , et al. October 11, 2 | 2005-10-11 |
Microprocessor architecture capable of supporting multiple heterogeneous processors
Grant 6,954,844 - Lentz , et al. October 11, 2 | 2005-10-11 |
High-performance, superscalar-based computer system with out-of-order instruction execution
Grant 6,948,052 - Nguyen , et al. September 20, 2 | 2005-09-20 |
High-performance, superscalar-based computer system with out-of-order instruction execution
Grant 6,941,447 - Nguyen , et al. September 6, 2 | 2005-09-06 |
High-performance, superscalar-based computer system with out-of-order instruction execution
Grant 6,934,829 - Nguyen , et al. August 23, 2 | 2005-08-23 |
High-performance, superscalar-based computer system with out-of-order instruction execution
Grant 6,915,412 - Nguyen , et al. July 5, 2 | 2005-07-05 |
Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip
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Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip
Grant 6,782,521 - Iadonato , et al. August 24, 2 | 2004-08-24 |
System and method for handling load and/or store operations in a superscalar microprocessor
App 20040128487 - Brashears, Cheryl Senter ; et al. | 2004-07-01 |
High-performance, superscalar-based computer system with out-of-order instruction execution
App 20040093485 - Nguyen, Le Trong ; et al. | 2004-05-13 |
High-performance, superscalar-based computer system with out-of-order instruction execution
App 20040093482 - Nguyen, Le-Trong ; et al. | 2004-05-13 |
High performance, superscalar-based computer system with out-of-order instruction execution
App 20040093483 - Nguyen, Le Trong ; et al. | 2004-05-13 |
High-performance, superscalar-based computer system with out-of-order intstruction execution
App 20040054872 - Nguyen, Le Trong ; et al. | 2004-03-18 |
Microprocessor architecture capable of supporting multiple heterogeneous processors
App 20040024987 - Lentz, Derek J. ; et al. | 2004-02-05 |
High-performance, superscalar-based computer system with out-of-order instruction execution
Grant 6,647,485 - Nguyen , et al. November 11, 2 | 2003-11-11 |
Microprocessor architecture capable of supporting multiple heterogeneous processors
Grant 6,611,908 - Lentz , et al. August 26, 2 | 2003-08-26 |
RISC microprocessor architecture implementing multiple typed register sets
App 20030115440 - Garg, Sanjiv ; et al. | 2003-06-19 |
System and method for translating non-native instructions to native instructions for processing on a host processor
App 20030084270 - Coon, Brett ; et al. | 2003-05-01 |
High-performance, superscalar-based computer system with out-of-order instruction execution
App 20030079113 - Nguyen, Le Trong ; et al. | 2003-04-24 |
High-performance, superscalar-based computer system with out-of-order instruction execution
App 20030070060 - Nguyen, Le Trong ; et al. | 2003-04-10 |
High-performance, superscalar-based computer system with out-of-order instruction execution
App 20030056086 - Nguyen, Le Trong ; et al. | 2003-03-20 |
High-performance, superscalar-based computer system with out-of-order instruction execution
App 20030056087 - Nguyen, Le Trong ; et al. | 2003-03-20 |
Superscalar RISC instruction scheduling
App 20030005260 - Garg, Sanjiv ; et al. | 2003-01-02 |
Data processing device with memory coupling unit
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Multiprocessor operation in a multimedia signal processor
Grant 6,425,054 - Nguyen July 23, 2 | 2002-07-23 |
Execution unit for processing a data stream independently and in parallel
Grant 6,401,194 - Nguyen , et al. June 4, 2 | 2002-06-04 |
Microprocessor architecture capable of supporting multiple heterogeneous processors
App 20020059508 - Lentz, Derek J. ; et al. | 2002-05-16 |
High-performance, superscalar-based computer system with out-of-order instruction execution
App 20020029328 - Nguyen, Le Trong ; et al. | 2002-03-07 |
High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution
App 20020016903 - Nguyen, Le Trong ; et al. | 2002-02-07 |
RISC microprocessor architecture implementing multiple register sets
App 20010034823 - Garg, Sanjiv ; et al. | 2001-10-25 |
Superscalar RISC instruction scheduling
Grant 6,289,433 - Garg , et al. September 11, 2 | 2001-09-11 |
High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution
Grant 6,282,630 - Nguyen , et al. August 28, 2 | 2001-08-28 |
High-performance, superscalar-based computer system with out-of-order instruction execution
Grant 6,272,619 - Nguyen , et al. August 7, 2 | 2001-08-07 |
Microprocessor architecture capable of supporting multiple heterogeneous processors
Grant 6,272,579 - Lentz , et al. August 7, 2 | 2001-08-07 |
System and method for translating non-native instructions to native instructions for processing on a host processor
Grant 6,263,423 - Coon , et al. July 17, 2 | 2001-07-17 |
High performance, superscalar-based computer system with out-of-order instruction execution
Grant 6,256,720 - Nguyen , et al. July 3, 2 | 2001-07-03 |
System and method for adjusting priorities associated with multiple devices seeking access to a memory array unit
Grant 6,219,763 - Lentz , et al. April 17, 2 | 2001-04-17 |
Computer system for processing multiple requests and out of order returns using a request queue
Grant 6,173,369 - Nguyen , et al. January 9, 2 | 2001-01-09 |
Shared bus system with transaction and destination ID
Grant 6,173,349 - Qureshi , et al. January 9, 2 | 2001-01-09 |
High-performance, superscalar-based computer system with out-of-order instruction execution
Grant 6,128,723 - Nguyen , et al. October 3, 2 | 2000-10-03 |
Single-instruction-multiple-data processing in a multimedia signal processor
Grant 6,058,465 - Nguyen May 2, 2 | 2000-05-02 |
High performance, superscalar-based computer system with out-of-order instruction execution
Grant 6,038,654 - Nguyen , et al. March 14, 2 | 2000-03-14 |
High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution
Grant 6,038,653 - Nguyen , et al. March 14, 2 | 2000-03-14 |
System and method for handling load and/or store operations in a superscalar microprocessor
Grant 5,987,593 - Senter , et al. November 16, 1 | 1999-11-16 |
Superscalar microprocessor for out-of-order and concurrently executing at least two RISC instructions translating from in-order CISC instructions
Grant 5,983,334 - Coon , et al. November 9, 1 | 1999-11-09 |
Coordination and synchronization of an asymmetric, single-chip, dual multiprocessor
Grant 5,978,838 - Mohamed , et al. November 2, 1 | 1999-11-02 |
Superscalar RISC instruction scheduling
Grant 5,974,526 - Garg , et al. October 26, 1 | 1999-10-26 |
DMA controller which receives size data for each DMA channel
Grant 5,974,480 - Qureshi , et al. October 26, 1 | 1999-10-26 |
Load and store unit for a vector processor
Grant 5,961,628 - Nguyen , et al. October 5, 1 | 1999-10-05 |
Instruction fetch unit including instruction buffer and secondary or branch target buffer that transfers prefetched instructions to the instruction buffer
Grant 5,889,986 - Nguyen , et al. March 30, 1 | 1999-03-30 |
Single-instruction-multiple-data processing using multiple banks of vector registers
Grant 5,838,984 - Nguyen , et al. November 17, 1 | 1998-11-17 |
RISC microprocessor architecture implementing multiple typed register sets
Grant 5,838,986 - Garg , et al. November 17, 1 | 1998-11-17 |
Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip
Grant 5,831,871 - Iadonato , et al. November 3, 1 | 1998-11-03 |
High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution
Grant 5,832,292 - Nguyen , et al. November 3, 1 | 1998-11-03 |
System and method for processing multiple requests and out of order returns
Grant 5,778,434 - Nguyen , et al. July 7, 1 | 1998-07-07 |
Multi processor system having dynamic priority based on row match of previously serviced address, number of times denied service and number of times serviced without interruption
Grant 5,754,800 - Lentz , et al. May 19, 1 | 1998-05-19 |
Superscalar risc instruction scheduling
Grant 5,737,624 - Garg , et al. April 7, 1 | 1998-04-07 |
High-performance superscalar-based computer system with out-of-order instruction execution
Grant 5,689,720 - Nguyen , et al. November 18, 1 | 1997-11-18 |
RISC microprocessor architecture implementing multiple typed register sets
Grant 5,682,546 - Garg , et al. October 28, 1 | 1997-10-28 |
System for translating non-native instructions to native instructions and combining them into a final bucket for processing on a host processor
Grant 5,619,666 - Coon , et al. April 8, 1 | 1997-04-08 |
Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU
Grant 5,604,865 - Lentz , et al. February 18, 1 | 1997-02-18 |
Apparatus and method for emulating a microelectronic device by interconnecting and running test vectors on physically implemented functional modules
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High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution
Grant 5,560,032 - Nguyen , et al. September 24, 1 | 1996-09-24 |
Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU
Grant 5,440,752 - Lentz , et al. August 8, 1 | 1995-08-08 |
System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
Grant 5,438,668 - Coon , et al. August 1, 1 | 1995-08-01 |
Page printer controller including a single chip superscalar microprocessor with graphics functional units
Grant 5,394,515 - Lentz , et al. February 28, 1 | 1995-02-28 |
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