Nguyen; Hien D.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Nguyen; Hien D..The latest application filed is for "three-dimensional chip-to-wafer integration".
- Nguyen; Hien D. - The Colony TX
| Patent | Date |
|---|---|
| Three-dimensional chip-to-wafer integration Grant 10,032,749 - Kelkar , et al. July 24, 2 | 2018-07-24 |
| Technique for wafer-level processing of QFN packages Grant 9,472,451 - Khandekar , et al. October 18, 2 | 2016-10-18 |
| Three-dimensional Chip-to-wafer Integration App 20160071826 - Kelkar; Amit S. ; et al. | 2016-03-10 |
| Wafer-level package device having high-standoff peripheral solder bumps Grant 9,219,043 - Kelkar , et al. December 22, 2 | 2015-12-22 |
| Three-dimensional chip-to-wafer integration Grant 9,190,391 - Kelkar , et al. November 17, 2 | 2015-11-17 |
| Technique For Wafer-level Processing Of Qfn Packages App 20150028475 - Khandekar; Viren ; et al. | 2015-01-29 |
| Techniques for wafer-level processing of QFN packages Grant 8,860,222 - Khandekar , et al. October 14, 2 | 2014-10-14 |
| Wafer-level Package Device Having High-standoff Peripheral Solder Bumps App 20140264845 - Kelkar; Amit S. ; et al. | 2014-09-18 |
| Techniques For Wafer-level Processing Of Qfn Packages App 20130161817 - Khandekar; Viren ; et al. | 2013-06-27 |
| Three-dimensional Chip-to-wafer Integration App 20130105966 - Kelkar; Amit Subhash ; et al. | 2013-05-02 |
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