loadpatents
name:-0.11736798286438
name:-0.054436922073364
name:-0.0016961097717285
Nguyen; Dung Quoc Patent Filings

Nguyen; Dung Quoc

Patent Applications and Registrations

Patent applications and USPTO patent grants for Nguyen; Dung Quoc.The latest application filed is for "parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries".

Company Profile
1.49.50
  • Nguyen; Dung Quoc - AUSTIN TX
  • Nguyen, Dung Quoc - Irvine CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Parallel Slice Processor Having A Recirculating Load-store Queue For Fast Deallocation Of Issue Queue Entries
App 20210406023 - Ayub; Salma ;   et al.
2021-12-30
Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries
Grant 11,150,907 - Ayub , et al. October 19, 2
2021-10-19
Linkable issue queue parallel execution slice processing method
Grant 10,223,125 - Brownscheidle , et al.
2019-03-05
Processor core including pre-issue load-hit-store (LHS) hazard prediction to reduce rejection of load instructions
Grant 10,209,995 - Chadha , et al. Feb
2019-02-19
Linkable Issue Queue Parallel Execution Slice Processing Method
App 20180336038 - Brownscheidle; Jeffrey Carl ;   et al.
2018-11-22
Parallel Slice Processor Having A Recirculating Load-store Queue For Fast Deallocation Of Issue Queue Entries
App 20180336036 - Ayub; Salma ;   et al.
2018-11-22
Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries
Grant 10,133,576 - Ayub , et al. November 20, 2
2018-11-20
Linkable issue queue parallel execution slice for a processor
Grant 10,133,581 - Brownscheidle , et al. November 20, 2
2018-11-20
Parallel Slice Processor Having A Recirculating Load-store Queue For Fast Deallocation Of Issue Queue Entries
App 20160202986 - Ayub; Salma ;   et al.
2016-07-14
Linkable Issue Queue Parallel Execution Slice For A Processor
App 20160202990 - Brownscheidle; Jeffrey Carl ;   et al.
2016-07-14
Linkable Issue Queue Parallel Execution Slice Processing Method
App 20160202992 - Brownscheidle; Jeffrey Carl ;   et al.
2016-07-14
Parallel Slice Processing Method Using A Recirculating Load-store Queue For Fast Deallocation Of Issue Queue Entries
App 20160202988 - Ayub; Salma ;   et al.
2016-07-14
Processing Method Including Pre-issue Load-hit-store (lhs) Hazard Prediction To Reduce Rejection Of Load Instructions
App 20160117174 - Chadha; Sundeep ;   et al.
2016-04-28
Processor Core Including Pre-issue Load-hit-store (lhs) Hazard Prediction To Reduce Rejection Of Load Instructions
App 20160117173 - Chadha; Sundeep ;   et al.
2016-04-28
Instruction tracking system for processors
Grant 8,521,998 - Abernathy , et al. August 27, 2
2013-08-27
Processor including age tracking of issue queue instructions
Grant 8,489,863 - Bishop , et al. July 16, 2
2013-07-16
Processor register recovery after flush operation
Grant 8,417,925 - Nguyen April 9, 2
2013-04-09
Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessors
Grant 8,418,180 - Bishop , et al. April 9, 2
2013-04-09
Processor including age tracking of issue queue instructions
Grant 8,380,964 - Bishop , et al. February 19, 2
2013-02-19
Multi-mode register rename mechanism that augments logical registers by switching a physical register from the register rename buffer when switching between in-order and out-of-order instruction processing in a simultaneous multi-threaded microprocessor
Grant 8,347,068 - Eickemeyer , et al. January 1, 2
2013-01-01
Processor Including Age Tracking of Issue Queue Instructions
App 20120260069 - Bishop; James Wilson ;   et al.
2012-10-11
Managing instructions for more efficient load/store unit usage
Grant 8,271,765 - Bose , et al. September 18, 2
2012-09-18
Processor register recovery after flush operation
Grant 8,245,018 - Nguyen August 14, 2
2012-08-14
Processor Register Recovery After Flush Operation
App 20120144164 - Nguyen; Dung Quoc
2012-06-07
Selecting fixed-point instructions to issue on load-store unit
Grant 8,108,655 - Abernathy , et al. January 31, 2
2012-01-31
Dependency tracking for enabling successive processor instructions to issue
Grant 8,086,826 - Brown , et al. December 27, 2
2011-12-27
Method to reduce power consumption of a register file with multi SMT support
Grant 8,046,566 - Abernathy , et al. October 25, 2
2011-10-25
Information handling system with real and virtual load/store instruction issue queue
Grant 8,041,928 - Burky , et al. October 18, 2
2011-10-18
Processor Including Age Tracking Of Issue Queue Instructions
App 20110185159 - Bishop; James Wilson ;   et al.
2011-07-28
Branch lookahead prefetch for microprocessors
Grant 7,877,580 - Eickemeyer , et al. January 25, 2
2011-01-25
Processor instruction retry recovery
Grant 7,827,443 - Eisen , et al. November 2, 2
2010-11-02
Managing Instructions For More Efficient Load/store Unit Usage
App 20100262808 - Bose; Pradip ;   et al.
2010-10-14
Selecting Fixed-Point Instructions to Issue on Load-Store Unit
App 20100250901 - Abernathy; Christopher Michael ;   et al.
2010-09-30
Dependency Tracking For Enabling Successive Processor Instructions To Issue
App 20100250900 - Brown; Mary Douglass ;   et al.
2010-09-30
Processor Register Recovery After Flush Operation
App 20100169622 - Nguyen; Dung Quoc
2010-07-01
Information Handling System With Real And Virtual Load/store Instruction Issue Queue
App 20100161945 - Burky; William E. ;   et al.
2010-06-24
Apparatus and method for providing multiple reads/writes using a 2Read/2Write register file array
Grant 7,663,963 - Chu , et al. February 16, 2
2010-02-16
Dynamic recalculation of resource vector at issue queue for steering of dependent instructions
Grant 7,650,486 - Le , et al. January 19, 2
2010-01-19
Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessors
Grant 7,631,308 - Bishop , et al. December 8, 2
2009-12-08
Method to Reduce Power Consumption of a Register File with Multi SMT Support
App 20090292892 - Abernathy; Christopher M. ;   et al.
2009-11-26
Using a modified value GPR to enhance lookahead prefetch
Grant 7,620,799 - Eickemeyer , et al. November 17, 2
2009-11-17
Methods to randomly or pseudo-randomly, without bias, select instruction for performance analysis in a microprocessor
Grant 7,620,801 - Bishop , et al. November 17, 2
2009-11-17
System and method for predictive early allocation of stores in a microprocessor
Grant 7,600,099 - Le , et al. October 6, 2
2009-10-06
Load lookahead prefetch for microprocessors
Grant 7,594,096 - Eickemeyer , et al. September 22, 2
2009-09-22
Branch lookahead prefetch for microprocessors
Grant 7,552,318 - Eickemeyer , et al. June 23, 2
2009-06-23
Processor Instruction Retry Recovery
App 20090063898 - Eisen; Susan Elizabeth ;   et al.
2009-03-05
Method using vector component comprising first and second bits to regulate movement of dependent instructions in a microprocessor
Grant 7,490,226 - Le , et al. February 10, 2
2009-02-10
Method for checkpointing instruction groups with out-of-order floating point instructions in a multi-threaded processor
Grant 7,478,276 - Bishop , et al. January 13, 2
2009-01-13
Processor instruction retry recovery
Grant 7,467,325 - Eisen , et al. December 16, 2
2008-12-16
Thread Priority Method for Ensuring Processing Fairness in Simultaneous Multi-Threading Microprocessors
App 20080294884 - Bishop; James Wilson ;   et al.
2008-11-27
Load lookahead prefetch for microprocessors
Grant 7,444,498 - Eickemeyer , et al. October 28, 2
2008-10-28
Using a Modified Value GPR to Enhance Lookahead Prefetch
App 20080250230 - Eickemeyer; Richard James ;   et al.
2008-10-09
Multi-Mode Register Rename Mechanism for a Highly Threaded Simultaneous Multi-Threaded Microprocessor
App 20080250226 - Eickemeyer; Richard James ;   et al.
2008-10-09
Apparatus and Method for Providing Multiple Reads/Writes Using a 2Read/2Write Register File Array
App 20080239860 - Chu; Sam Gat-Shang ;   et al.
2008-10-02
Configurable Microprocessor
App 20080229065 - Le; Hung Qui ;   et al.
2008-09-18
Configurable Microprocessor
App 20080229058 - Le; Hung Qui ;   et al.
2008-09-18
System and Method for Predictive Early Allocation of Stores in a Microprocessor
App 20080222395 - Le; Hung Qui ;   et al.
2008-09-11
Using a modified value GPR to enhance lookahead prefetch
Grant 7,421,567 - Eickemeyer , et al. September 2, 2
2008-09-02
Method for providing multiple reads/writes using a 2read/2write register file array
Grant 7,400,548 - Chu , et al. July 15, 2
2008-07-15
Branch lookahead prefetch for microprocessors
App 20080091928 - Eickemeyer; Richard James ;   et al.
2008-04-17
Load Lookahead Prefetch for Microprocessors
App 20080077776 - Eickemeyer; Richard James ;   et al.
2008-03-27
Apparatus, system and method for quickly determining an oldest instruction in a non-moving instruction queue
Grant 7,302,553 - Chu , et al. November 27, 2
2007-11-27
Method and logical apparatus for rename register reallocation in a simultaneous multi-threaded (SMT) processor
Grant 7,290,261 - Burky , et al. October 30, 2
2007-10-30
Method and apparatus for dynamic modification of microprocessor instruction group at dispatch
Grant 7,254,697 - Bishop , et al. August 7, 2
2007-08-07
Apparatus and method for speeding up access time of a large register file with wrap capability
Grant 7,243,209 - Chu , et al. July 10, 2
2007-07-10
Instruction group formation and mechanism for SMT dispatch
Grant 7,237,094 - Curran , et al. June 26, 2
2007-06-26
System and method for performing floating point store folding
Grant 7,188,233 - Haess , et al. March 6, 2
2007-03-06
Thread priority method, apparatus, and computer program product for ensuring processing fairness in simultaneous multi-threading microprocessors
App 20060184946 - Bishop; James Wilson ;   et al.
2006-08-17
Methods to randomly or pseudo-randomly, without bias, select instruction for performance analysis in a microprocessor
App 20060184776 - Bishop; James Wilson ;   et al.
2006-08-17
System and method for processing limited out-of-order execution of floating point loads
App 20060179286 - Haess; Juergen ;   et al.
2006-08-10
Method for checkpointing instruction groups with out-of-order floating point instructions in a multi-threaded processor
App 20060179346 - Bishop; James Wilson ;   et al.
2006-08-10
System and method for performing floating point store folding
App 20060179100 - Haess; Juergen ;   et al.
2006-08-10
Apparatus and method for providing multiple reads/writes using a 2read/2write register file array
App 20060179257 - Chu; Sam Gat-Shang ;   et al.
2006-08-10
Processor instruction retry recovery
App 20060179207 - Eisen; Susan Elizabeth ;   et al.
2006-08-10
Method using hazard vector to enhance issue throughput of dependent instructions in a microprocessor
App 20060179282 - Le; Hung Qui ;   et al.
2006-08-10
Apparatus and method for speeding up access time of a large register file with wrap capability
App 20060171208 - Chu; Sam Gat-Shang ;   et al.
2006-08-03
Apparatus and method for dependency tracking and register file bypass controls using a scannable register file
App 20060168393 - Christensen; Bjorn Peter ;   et al.
2006-07-27
Using a modified value GPR to enhance lookahead prefetch
App 20060149934 - Eickemever; Richard James ;   et al.
2006-07-06
Load lookahead prefetch for microprocessors
App 20060149935 - Eickemeyer; Richard James ;   et al.
2006-07-06
Branch lookahead prefetch for microprocessors
App 20060149933 - Eickemeyer; Richard James ;   et al.
2006-07-06
Instruction group formation and mechanism for SMT dispatch
App 20060101241 - Curran; Brian William ;   et al.
2006-05-11
Mechanism for effectively handling livelocks in a simultaneous multithreading processor
Grant 7,000,047 - Nguyen , et al. February 14, 2
2006-02-14
Completion monitoring in a processor having multiple execution units with various latencies
Grant 6,826,678 - Le , et al. November 30, 2
2004-11-30
Mechanism for effectively handling livelocks in a simultaneous multithreading processor
App 20040215933 - Nguyen, Dung Quoc ;   et al.
2004-10-28
Method and logical apparatus for rename register reallocation in a simultaneous multi-threaded (SMT) processor
App 20040216120 - Burky, William Elton ;   et al.
2004-10-28
Apparatus, system and method for quickly determining an oldest instruction in a non-moving instruction queue
App 20040148493 - Chu, Sam Gat-Shang ;   et al.
2004-07-29
High-speed digital subscriber line (HDSL) wander reduction
App 20040017848 - Doan, Harrison ;   et al.
2004-01-29
High-speed digital subscriber line (HDSL) wander reduction utilizing minimums
App 20040017822 - Doan, Harrison ;   et al.
2004-01-29
Completion monitoring in a processor having multiple execution units with various latencies
App 20030196074 - Le, Hung Qui ;   et al.
2003-10-16
Method for limiting physical resource usage in a virtual tag allocation environment of a microprocessor
App 20030182540 - Burky, William Elton ;   et al.
2003-09-25
Method and apparatus for fast operand access stage in a CPU design using a cache-like structure
App 20020124157 - Le, Hung Qui ;   et al.
2002-09-05
Methods and apparatus for exploiting virtual buffers to increase instruction parallelism in a pipelined processor
Grant 6,298,435 - Chan , et al. October 2, 2
2001-10-02
Obtaining load target operand pre-fetch address from history table information upon incremented number of access indicator threshold
Grant 6,275,918 - Burky , et al. August 14, 2
2001-08-14
Data processing system having an apparatus for exception tracking during out-of-order operation and method therefor
Grant 6,128,722 - Fry , et al. October 3, 2
2000-10-03

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