| Patent | Date |
|---|
Steering a history buffer entry to a specific recovery port during speculative flush recovery lookup in a processor
Grant 11,403,109 - Battle , et al. August 2, 2 | 2022-08-02 |
Program counter (PC)-relative load and store addressing for fused instructions
Grant 11,392,386 - Orzol , et al. July 19, 2 | 2022-07-19 |
Completion mechanism for a microprocessor instruction completion table
Grant 11,366,671 - Ward , et al. June 21, 2 | 2022-06-21 |
Slice-based allocation history buffer
Grant 11,360,775 - Barrick , et al. June 14, 2 | 2022-06-14 |
Logical register recovery within a processor
Grant 11,360,779 - Battle , et al. June 14, 2 | 2022-06-14 |
Assignment Of Microprocessor Register Tags At Issue Time
App 20220147359 - Battle; Steven J. ; et al. | 2022-05-12 |
Instruction dispatch routing
Grant 11,327,766 - Schwarz , et al. May 10, 2 | 2022-05-10 |
Processor providing intelligent management of values buffered in overlaid architected and non-architected register files
Grant 11,327,757 - Battle , et al. May 10, 2 | 2022-05-10 |
Instruction streaming using state migration
Grant 11,301,254 - Battle , et al. April 12, 2 | 2022-04-12 |
Finish status reporting for a simultaneous multithreading processor using an instruction completion table
Grant 11,269,647 - Ward , et al. March 8, 2 | 2022-03-08 |
Compaction Of Architected Registers In A Simultaneous Multithreading Processor
App 20220066830 - Battle; Steven J. ; et al. | 2022-03-03 |
Thread transition management
Grant 11,256,507 - Abernathy , et al. February 22, 2 | 2022-02-22 |
Instruction Handling For Accumulation Of Register Results In A Microprocessor
App 20220050682 - Thompto; Brian W. ; et al. | 2022-02-17 |
Program Counter (pc)-relative Load And Store Addressing
App 20220050684 - Orzol; Nicholas R. ; et al. | 2022-02-17 |
Handling And Fusing Load Instructions In A Processor
App 20220050679 - Lloyd; Bryan ; et al. | 2022-02-17 |
Handling and fusing load instructions in a processor
Grant 11,249,757 - Lloyd , et al. February 15, 2 | 2022-02-15 |
On-the-fly Adjustment Of Issue-write Back Latency To Avoid Write Back Collisions Using A Result Buffer
App 20220035637 - Barrick; Brian D. ; et al. | 2022-02-03 |
Instruction Dispatch Routing
App 20220035636 - Schwarz; Eric Mark ; et al. | 2022-02-03 |
Microprocessor That Fuses Load And Compare Instructions
App 20220035634 - Lloyd; Bryan ; et al. | 2022-02-03 |
Fusion Of Microprocessor Store Instructions
App 20220019436 - Lloyd; Bryan ; et al. | 2022-01-20 |
Fused overloaded register file read to enable 2-cycle move from condition register instruction in a microprocessor
Grant 11,194,578 - Battle , et al. December 7, 2 | 2021-12-07 |
System and handling of register data in processors
Grant 11,188,332 - Battle , et al. November 30, 2 | 2021-11-30 |
Multiple streams execution for hard-to-predict branches in a microprocessor
Grant 11,188,340 - Thompto , et al. November 30, 2 | 2021-11-30 |
Pairing issue queues for complex instructions and instruction fusion
Grant 11,182,164 - Barrick , et al. November 23, 2 | 2021-11-23 |
Processor Providing Intelligent Management Of Values Buffered In Overlaid Architected And Non-architected Register Files
App 20210342150 - Battle; Steven J. ; et al. | 2021-11-04 |
Fusion to enhance early address generation of load instructions in a microprocessor
Grant 11,163,571 - Barrick , et al. November 2, 2 | 2021-11-02 |
Implementing write ports in register-file array cell
Grant 11,163,568 - Islam , et al. November 2, 2 | 2021-11-02 |
Thread-based organization of slice target register file entry in a microprocessor to permit writing scalar or vector data to portions of a single register file entry
Grant 11,157,276 - Battle , et al. October 26, 2 | 2021-10-26 |
Energy efficient source operand issue
Grant 11,150,909 - Brownscheidle , et al. October 19, 2 | 2021-10-19 |
Independent mapping of threads
Grant 11,144,323 - Chu , et al. October 12, 2 | 2021-10-12 |
Redistribution of architected states for a processor register file
Grant 11,144,319 - Battle , et al. October 12, 2 | 2021-10-12 |
Supporting speculative microprocessor instruction execution
Grant 11,144,364 - Battle , et al. October 12, 2 | 2021-10-12 |
Operation of a multi-slice processor implementing a hardware level transfer of an execution thread
Grant 11,138,050 - Barrick , et al. October 5, 2 | 2021-10-05 |
Instruction handling for accumulation of register results in a microprocessor
Grant 11,132,198 - Thompto , et al. September 28, 2 | 2021-09-28 |
Check pointing of accumulator register results in a microprocessor
Grant 11,119,772 - Battle , et al. September 14, 2 | 2021-09-14 |
Slice-target register file for microprocessor
Grant 11,119,774 - Thompto , et al. September 14, 2 | 2021-09-14 |
Decoupling of conditional branches
Grant 11,106,466 - Orzol , et al. August 31, 2 | 2021-08-31 |
Banked slice-target register file for wide dataflow execution in a microprocessor
Grant 11,093,246 - Boersma , et al. August 17, 2 | 2021-08-17 |
Register file write using pointers
Grant 11,093,282 - Barrick , et al. August 17, 2 | 2021-08-17 |
Prioritized instructions in an instruction completion table of a simultaneous multithreading processor
Grant 11,068,274 - Ward , et al. July 20, 2 | 2021-07-20 |
High bandwidth logical register flush recovery
Grant 11,068,267 - Battle , et al. July 20, 2 | 2021-07-20 |
Instruction streaming using copy select vector
Grant 11,061,681 - Battle , et al. July 13, 2 | 2021-07-13 |
Check Pointing Of Accumulator Register Results In A Microprocessor
App 20210173649 - Battle; Steven J ; et al. | 2021-06-10 |
On-demand multi-tiered hang buster for SMT microprocessor
Grant 11,030,018 - Battle , et al. June 8, 2 | 2021-06-08 |
Saving and restoring a transaction memory state
Grant 10,996,995 - Battle , et al. May 4, 2 | 2021-05-04 |
Program instruction scheduling
Grant 10,983,797 - Zoellin , et al. April 20, 2 | 2021-04-20 |
Instruction completion table with ready-to-complete vector
Grant 10,977,034 - Ward , et al. April 13, 2 | 2021-04-13 |
Parallel dispatching of multi-operation instructions in a multi-slice computer processor
Grant 10,970,079 - Feiste , et al. April 6, 2 | 2021-04-06 |
Logical Register Recovery Within A Processor
App 20210089322 - Battle; Steven J. ; et al. | 2021-03-25 |
System and handling of register data in processors
Grant 10,956,158 - Battle , et al. March 23, 2 | 2021-03-23 |
Logical register recovery within a processor
Grant 10,949,213 - Battle , et al. March 16, 2 | 2021-03-16 |
Implementation of execution compression of instructions in slice target register file mapper
Grant 10,949,205 - Bowman , et al. March 16, 2 | 2021-03-16 |
Banked Slice-target Register File For Wide Dataflow Execution In A Microprocessor
App 20210072991 - Boersma; Maarten J. ; et al. | 2021-03-11 |
Thread-based Organization Of Slice Target Register File Entry In A Microprocessor
App 20210072993 - Battle; Steven J. ; et al. | 2021-03-11 |
Slice-target Register File For Microprocessor
App 20210072992 - Thompto; Brian W. ; et al. | 2021-03-11 |
Fast multi-width instruction issue in parallel slice processor
Grant 10,942,745 - Ayub , et al. March 9, 2 | 2021-03-09 |
Instruction Handling For Accumulation Of Register Results In A Microprocessor
App 20210064365 - Thompto; Brian W. ; et al. | 2021-03-04 |
Instruction chaining
Grant 10,936,321 - Feiste , et al. March 2, 2 | 2021-03-02 |
Speculatively releasing store data before store instruction completion in a processor
Grant 10,929,144 - Ward , et al. February 23, 2 | 2021-02-23 |
Issue queue snooping for asynchronous flush and restore of distributed history buffer
Grant 10,909,034 - Terry , et al. February 2, 2 | 2021-02-02 |
Instruction Streaming Using Copy Select Vector
App 20210026643 - Battle; Steven J. ; et al. | 2021-01-28 |
Instruction Streaming Using State Migration
App 20210026642 - Battle; Steven J. ; et al. | 2021-01-28 |
Speculative execution of both paths of a weakly predicted branch instruction
Grant 10,901,743 - Ward , et al. January 26, 2 | 2021-01-26 |
Handling unaligned load operations in a multi-slice computer processor
Grant 10,884,742 - Chadha , et al. January 5, 2 | 2021-01-05 |
Slice-based allocation history buffer
Grant 10,884,752 - Barrick , et al. January 5, 2 | 2021-01-05 |
Dispatching, allocating, and deallocating instructions with real/virtual and region tags in a queue in a processor
Grant 10,877,763 - Lloyd , et al. December 29, 2 | 2020-12-29 |
Program Instruction Scheduling
App 20200379766 - Zoellin; Christian ; et al. | 2020-12-03 |
Parallel slice processor shadowing states of hardware threads across execution slices
Grant 10,838,728 - Feiste , et al. November 17, 2 | 2020-11-17 |
System And Handling Of Register Data In Processors
App 20200356366 - Battle; Steven J. ; et al. | 2020-11-12 |
System And Handling Of Register Data In Processors
App 20200356369 - Battle; Steven J. ; et al. | 2020-11-12 |
Handling unaligned load operations in a multi-slice computer processor
Grant 10,831,481 - Chadha , et al. November 10, 2 | 2020-11-10 |
Mechanism for completing atomic instructions in a microprocessor
Grant 10,831,489 - Ward , et al. November 10, 2 | 2020-11-10 |
Method to execute successive dependent instructions from an instruction stream in a processor
Grant 10,831,496 - Boersma , et al. November 10, 2 | 2020-11-10 |
Managing an issue queue for fused instructions and paired instructions in a microprocessor
Grant 10,831,501 - Genden , et al. November 10, 2 | 2020-11-10 |
Most favored branch issue
Grant 10,831,492 - Ayub , et al. November 10, 2 | 2020-11-10 |
Managing an issue queue for fused instructions and paired instructions in a microprocessor
Grant 10,831,498 - Genden , et al. November 10, 2 | 2020-11-10 |
High Bandwidth Logical Register Flush Recovery
App 20200341767 - Battle; Steven J. ; et al. | 2020-10-29 |
Register File Write Using Pointers
App 20200326978 - Barrick; Brian D. ; et al. | 2020-10-15 |
Saving And Restoring A Transaction Memory State
App 20200301758 - BATTLE; Steven J. ; et al. | 2020-09-24 |
Prioritization protocols of conditional branch instructions
Grant 10,776,122 - Genden , et al. Sept | 2020-09-15 |
Method To Execute Successive Dependent Instructions From An Instruction Stream In A Processor
App 20200278868 - Boersma; Maarten J. ; et al. | 2020-09-03 |
Instruction completion table containing entries that share instruction tags
Grant 10,761,856 - Ward , et al. Sep | 2020-09-01 |
Dual compare of least-significant-bit for dependency wake up from a fused instruction tag in a microprocessor
Grant 10,747,545 - Genden , et al. A | 2020-08-18 |
Operation of a multi-slice processor implementing load-hit-store handling
Grant 10,740,107 - Ayub , et al. A | 2020-08-11 |
Flush-recovery bandwidth in a processor
Grant 10,740,140 - Battle , et al. A | 2020-08-11 |
Instruction Chaining
App 20200249954 - Kind Code | 2020-08-06 |
Speculatively Releasing Stores in a Processor
App 20200249946 - Kind Code | 2020-08-06 |
Completion Mechanism For A Microprocessor Instruction Completion Table
App 20200241880 - WARD; Kenneth L. ; et al. | 2020-07-30 |
Supporting Speculative Microprocessor Instruction Execution
App 20200241931 - Battle; Steven J. ; et al. | 2020-07-30 |
Completion mechanism for a microprocessor instruction completion table
Grant 10,725,786 - Ward , et al. | 2020-07-28 |
Merging status and control data in a reservation station
Grant 10,719,056 - Barrick , et al. | 2020-07-21 |
Slice-based Allocation History Buffer
App 20200225957 - Barrick; Brian D. ; et al. | 2020-07-16 |
Mechanism to stop completions using stop codes in an instruction completion table
Grant 10,713,057 - Ward , et al. | 2020-07-14 |
Implementation Of Execution Compression Of Instructions In Slice Target Register File Mapper
App 20200201639 - Bowman; Joshua ; et al. | 2020-06-25 |
Multiple Streams Execution For Branch Predication In A Microprocessor
App 20200201646 - THOMPTO; Brian W. ; et al. | 2020-06-25 |
Logical Register Recovery Within A Processor
App 20200183700 - Battle; Steven J. ; et al. | 2020-06-11 |
Speculative Flush Recovery Lookup In A Processor
App 20200183701 - Battle; Steven J. ; et al. | 2020-06-11 |
Dual Compare Of Least-significant-bit For Dependency Wake Up From A Fused Instruction Tag In A Microprocessor
App 20200167166 - Genden; Michael J. ; et al. | 2020-05-28 |
Speeding up younger store instruction execution after a sync instruction
Grant 10,664,275 - Eisen , et al. | 2020-05-26 |
Flush-recovery Bandwidth In A Processor
App 20200159564 - Battle; Steven J. ; et al. | 2020-05-21 |
Variable latency pipe for interleaving instruction tags in a microprocessor
Grant 10,649,779 - Ayub , et al. | 2020-05-12 |
Instruction Completion Table With Ready-to-complete Vector
App 20200142697 - Ward; Kenneth L. ; et al. | 2020-05-07 |
Shared compare lanes for dependency wake up in a pair-based issue queue
Grant 10,635,444 - Genden , et al. | 2020-04-28 |
Variable latency pipe for interleaving instruction tags in a microprocessor
Grant 10,613,868 - Ayub , et al. | 2020-04-07 |
Data-less history buffer with banked restore ports in a register mapper
Grant 10,592,422 - Barrick , et al. | 2020-03-17 |
Implementing Write Ports in Register-File Array Cell
App 20200081713 - Islam; Saiful ; et al. | 2020-03-12 |
Independent Mapping Of Threads
App 20200073668 - Chu; Sam G. ; et al. | 2020-03-05 |
Completion Mechanism For A Microprocessor Instruction Completion Table
App 20200065102 - WARD; Kenneth L. ; et al. | 2020-02-27 |
Mechanism For Completing Atomic Instructions In A Microprocessor
App 20200065103 - WARD; Kenneth L. ; et al. | 2020-02-27 |
Mechanism To Stop Completions Using Stop Codes In An Instruction Completion Table
App 20200065110 - WARD; Kenneth L. ; et al. | 2020-02-27 |
Reducing power consumption in a multi-slice computer processor
Grant 10,564,691 - Battle , et al. Feb | 2020-02-18 |
Low Power Back-to-back Wake Up And Issue For Paired Issue Queue In A Microprocessor
App 20200042321 - Genden; Michael J. ; et al. | 2020-02-06 |
Dispatching, Allocating, and Deallocating Instructions in a Queue in a Processor
App 20200042319 - Lloyd; Bryan ; et al. | 2020-02-06 |
Parallel Dispatching Of Multi-operation Instructions In A Multi-slice Computer Processor
App 20200042320 - FEISTE; KURT A. ; et al. | 2020-02-06 |
Efficiently managing speculative finish tracking and error handling for load instructions
Grant 10,552,165 - Eisen , et al. Fe | 2020-02-04 |
Independent mapping of threads
Grant 10,545,762 - Chu , et al. Ja | 2020-01-28 |
Multi-level history buffer for transaction memory in a microprocessor
Grant 10,545,765 - Barrick , et al. Ja | 2020-01-28 |
Speculative Execution Of Both Paths Of A Weakly Predicted Branch Instruction
App 20200026520 - WARD; Kenneth L. ; et al. | 2020-01-23 |
Instruction Completion Table Containing Entries That Share Instruction Tags
App 20200026521 - WARD; Kenneth L. ; et al. | 2020-01-23 |
Multiple Level History Buffer for Transaction Memory Support
App 20200019405 - Battle; Steven J. ; et al. | 2020-01-16 |
Most Favored Branch Issue
App 20200012496 - Ayub; Salma ; et al. | 2020-01-09 |
Shared Compare Lanes For Dependency Wake Up In A Pair-based Issue Queue
App 20200004546 - GENDEN; MICHAEL J. ; et al. | 2020-01-02 |
Prioritization Protocols of Conditional Branch Instructions
App 20190384611 - Genden; Michael J. ; et al. | 2019-12-19 |
Decoupling Of Conditional Branches
App 20190384607 - Orzol; Nicholas R. ; et al. | 2019-12-19 |
Handling Unaligned Load Operations In A Multi-slice Computer Processor
App 20190384602 - CHADHA; SUNDEEP ; et al. | 2019-12-19 |
Parallel dispatching of multi-operation instructions in a multi-slice computer processor
Grant 10,496,412 - Feiste , et al. De | 2019-12-03 |
Handling unaligned load operations in a multi-slice computer processor
Grant 10,496,406 - Chadha , et al. De | 2019-12-03 |
Fused Overloaded Register File Read to Enable 2-Cycle Move from Condition Register Instruction in a Microprocessor
App 20190361698 - Battle; Steven J. ; et al. | 2019-11-28 |
On-demand GPR ECC error detection and scrubbing for a multi-slice microprocessor
Grant 10,489,253 - Battle , et al. Nov | 2019-11-26 |
Broadcasting messages between execution slices for issued instructions indicating when execution results are ready
Grant 10,445,100 - Ayub , et al. Oc | 2019-10-15 |
Efficiently managing speculative finish tracking and error handling for load instructions
Grant 10,423,423 - Eisen , et al. Sept | 2019-09-24 |
Handling Unaligned Load Operations In A Multi-slice Computer Processor
App 20190286446 - CHADHA; SUNDEEP ; et al. | 2019-09-19 |
Handling unaligned load operations in a multi-slice computer processor
Grant 10,409,598 - Chadha , et al. Sept | 2019-09-10 |
Managing An Issue Queue For Fused Instructions And Paired Instructions In A Microprocessor
App 20190265979 - GENDEN; MICHAEL J. ; et al. | 2019-08-29 |
Managing An Issue Queue For Fused Instructions And Paired Instructions In A Microprocessor
App 20190265978 - GENDEN; MICHAEL J. ; et al. | 2019-08-29 |
Managing an issue queue for fused instructions and paired instructions in a microprocessor
Grant 10,394,565 - Genden , et al. A | 2019-08-27 |
Managing an issue queue for fused instructions and paired instructions in a microprocessor
Grant 10,387,147 - Genden , et al. A | 2019-08-20 |
Processor For Avoiding Reduced Performance Using Instruction Metadata To Determine Not To Maintain A Mapping Of A Logical Regist
App 20190250913 - Abernathy; Christopher M ; et al. | 2019-08-15 |
Thread Transition Management
App 20190250918 - Abernathy; Christopher M. ; et al. | 2019-08-15 |
Asynchronous flush and restore of distributed history buffer
Grant 10,379,867 - Terry , et al. A | 2019-08-13 |
Operation Of A Multi-slice Processor Implementing A Hardware Level Transfer Of An Execution Thread
App 20190213055 - BARRICK; BRIAN D. ; et al. | 2019-07-11 |
Data-less History Buffer With Banked Restore Ports In A Register Mapper
App 20190188140 - Barrick; Brian D. ; et al. | 2019-06-20 |
Prioritized Instructions In An Instruction Completion Table Of A Simultaneous Multithreading Processor
App 20190187992 - WARD; Kenneth L. ; et al. | 2019-06-20 |
Finish Status Reporting For A Simultaneous Multithreading Processor Using An Instruction Completion Table
App 20190187993 - WARD; Kenneth L. ; et al. | 2019-06-20 |
Asynchronous Flush And Restore Of Distributed History Buffer
App 20190187995 - TERRY; David R. ; et al. | 2019-06-20 |
Issue Queue Snooping For Asynchronous Flush And Restore Of Distributed History Buffer
App 20190188133 - TERRY; David R. ; et al. | 2019-06-20 |
Operation of a multi-slice processor implementing dependency accumulation instruction sequencing
Grant 10,318,294 - Adeeb , et al. | 2019-06-11 |
Operation of a multi-slice processor implementing a hardware level transfer of an execution thread
Grant 10,318,356 - Barrick , et al. | 2019-06-11 |
On-demand Multi-tiered Hang Buster For Smt Microprocessor
App 20190171569 - BATTLE; Steven J. ; et al. | 2019-06-06 |
Slice-based Allocation History Buffer
App 20190163480 - Barrick; Brian D. ; et al. | 2019-05-30 |
Thread transition management
Grant 10,296,339 - Abernathy , et al. | 2019-05-21 |
Preventing premature reads from a general purpose register
Grant 10,296,337 - Battle , et al. | 2019-05-21 |
Method and apparatus for execution of threads on processing slices using a history buffer for recording architected register data
Grant 10,289,415 - Eisen , et al. | 2019-05-14 |
Method and apparatus for execution of threads on processing slices using a history buffer for restoring architected register data via issued instructions
Grant 10,282,205 - Eisen , et al. | 2019-05-07 |
Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instruction
Grant 10,282,207 - Barrick , et al. | 2019-05-07 |
Processor for avoiding reduced performance using instruction metadata to determine not to maintain a mapping of a logical register to a physical register in a first level register file
Grant 10,275,251 - Abernathy , et al. | 2019-04-30 |
Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instruction
Grant 10,268,482 - Barrick , et al. | 2019-04-23 |
Method and apparatus for managing a speculative transaction in a processing unit
Grant 10,255,071 - Ayub , et al. | 2019-04-09 |
Operation of a multi-slice processor with reduced flush and restore latency
Grant 10,248,421 - Ayub , et al. | 2019-04-02 |
Direct register restore mechanism for distributed history buffers
Grant 10,248,426 - Barrick , et al. | 2019-04-02 |
Split-level history buffer in a computer processing unit
Grant 10,241,800 - Le , et al. | 2019-03-26 |
Operation of a multi-slice processor with reduced flush and restore latency
Grant 10,241,790 - Ayub , et al. | 2019-03-26 |
ECC scrubbing method in a multi-slice microprocessor
Grant 10,223,196 - Barrick , et al. | 2019-03-05 |
Reducing power consumption in a multi-slice computer processor
Grant 10,209,757 - Battle , et al. Feb | 2019-02-19 |
Managing An Issue Queue For Fused Instructions And Paired Instructions In A Microprocessor
App 20190042238 - GENDEN; MICHAEL J. ; et al. | 2019-02-07 |
Managing An Issue Queue For Fused Instructions And Paired Instructions In A Microprocessor
App 20190042239 - GENDEN; MICHAEL J. ; et al. | 2019-02-07 |
Fast Multi-width Instruction Issue In Parallel Slice Processor
App 20190026113 - Ayub; Salma ; et al. | 2019-01-24 |
Rotational Dispatch For Parallel Slice Processor
App 20190026112 - Feiste; Kurt A. ; et al. | 2019-01-24 |
Speeding Up Younger Store Instruction Execution After a Sync Instruction
App 20190012175 - Eisen; Susan E. ; et al. | 2019-01-10 |
Mechanism for using a reservation station as a scratch register
Grant 10,175,985 - Chadha , et al. J | 2019-01-08 |
Partial ECC mechanism for a byte-write capable register
Grant 10,176,038 - Jeganathan , et al. J | 2019-01-08 |
Thread Transition Management
App 20180349141 - Abernathy; Christopher M. ; et al. | 2018-12-06 |
Operation of a multi-slice processor with selective producer instruction types
Grant 10,140,127 - Barrick , et al. Nov | 2018-11-27 |
On-demand Gpr Ecc Error Detection And Scrubbing For A Multi-slice Microprocessor
App 20180336108 - BATTLE; Steven J. ; et al. | 2018-11-22 |
Multi-level History Buffer For Transaction Memory In A Microprocessor
App 20180336037 - BARRICK; Brian D. ; et al. | 2018-11-22 |
Operation of a multi-slice processor implementing adaptive failure state capture
Grant 10,127,121 - Adeeb , et al. November 13, 2 | 2018-11-13 |
Operation of a multi-slice processor with selective producer instruction types
Grant 10,127,047 - Barrick , et al. November 13, 2 | 2018-11-13 |
Fast multi-width instruction issue in parallel slice processor
Grant 10,120,693 - Ayub , et al. November 6, 2 | 2018-11-06 |
History buffer with single snoop tag for multiple-field registers
Grant 10,108,423 - Genden , et al. October 23, 2 | 2018-10-23 |
Handling Unaligned Load Operations In A Multi-slice Computer Processor
App 20180300136 - CHADHA; SUNDEEP ; et al. | 2018-10-18 |
Handling Unaligned Load Operations In A Multi-slice Computer Processor
App 20180300135 - CHADHA; SUNDEEP ; et al. | 2018-10-18 |
Parallel slice processor shadowing states of hardware threads across execution slices
Grant 10,102,001 - Feiste , et al. October 16, 2 | 2018-10-16 |
Techniques to wake-up dependent instructions for back-to-back issue in a microprocessor
Grant 10,078,516 - Brownscheidle , et al. September 18, 2 | 2018-09-18 |
Handling unaligned load operations in a multi-slice computer processor
Grant 10,073,697 - Chadha , et al. September 11, 2 | 2018-09-11 |
Processing instructions in parallel with waw hazards and via a distributed history buffer in a microprocessor having a multi-execution slice architecture
Grant 10,073,699 - Eisen , et al. September 11, 2 | 2018-09-11 |
History buffer with hybrid entry support for multiple-field registers
Grant 10,067,766 - Genden , et al. September 4, 2 | 2018-09-04 |
Speeding up younger store instruction execution after a sync instruction
Grant 10,067,765 - Eisen , et al. September 4, 2 | 2018-09-04 |
Handling unaligned load operations in a multi-slice computer processor
Grant 10,067,763 - Chadha , et al. September 4, 2 | 2018-09-04 |
Thread transition management
Grant 10,055,226 - Abernathy , et al. August 21, 2 | 2018-08-21 |
Operation Of A Multi-slice Processor With Selective Producer Instruction Types
App 20180232230 - Barrick; Brian D. ; et al. | 2018-08-16 |
Operation Of A Multi-slice Processor With Selective Producer Instruction Types
App 20180232236 - BARRICK; BRIAN D. ; et al. | 2018-08-16 |
Parallel Slice Processor Shadowing States Of Hardware Threads Across Execution Slices
App 20180217842 - Feiste; Kurt A. ; et al. | 2018-08-02 |
Fast Multi-width Instruction Issue In Parallel Slice Processor
App 20180217843 - Ayub; Salma ; et al. | 2018-08-02 |
Adaptive debug tracing for microprocessors
Grant 10,037,259 - Adeeb , et al. July 31, 2 | 2018-07-31 |
Operation of a multi-slice processor implementing a mechanism to overcome a system hang
Grant 10,031,757 - Brownscheidle , et al. July 24, 2 | 2018-07-24 |
Universal history buffer to support multiple register types
Grant 9,996,353 - Genden , et al. June 12, 2 | 2018-06-12 |
Fast multi-width instruction issue in parallel slice processor
Grant 9,996,359 - Ayub , et al. June 12, 2 | 2018-06-12 |
Generating ECC values for byte-write capable registers
Grant 9,985,655 - Jeganathan , et al. May 29, 2 | 2018-05-29 |
Operation of a multi-slice processor implementing dynamic switching of instruction issuance order
Grant 9,983,879 - Brownscheidle , et al. May 29, 2 | 2018-05-29 |
Generating ECC values for byte-write capable registers
Grant 9,985,656 - Jeganathan , et al. May 29, 2 | 2018-05-29 |
Execution slice with supplemental instruction port for an instruction using a source operand from another instruction port
Grant 9,977,677 - Feiste , et al. May 22, 2 | 2018-05-22 |
Techniques to wake-up dependent instructions for back-to-back issue in a microprocessor
Grant 9,971,600 - Brownscheidle , et al. May 15, 2 | 2018-05-15 |
History buffer for multiple-field registers
Grant 9,971,604 - Chadha , et al. May 15, 2 | 2018-05-15 |
Operation of a multi-slice processor with history buffers storing transaction memory state information
Grant 9,971,687 - Barrick , et al. May 15, 2 | 2018-05-15 |
Age based fast instruction issue
Grant 9,965,286 - Brownscheidle , et al. May 8, 2 | 2018-05-08 |
Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor
Grant 9,959,123 - Bowman , et al. May 1, 2 | 2018-05-01 |
Bypassing a higher level register file in a processor having a multi-level register file and a set of bypass registers
Grant 9,959,121 - Abernathy , et al. May 1, 2 | 2018-05-01 |
Operation of a multi-slice processor with selective producer instruction types
Grant 9,952,861 - Barrick , et al. April 24, 2 | 2018-04-24 |
Operation of a multi-slice processor with selective producer instruction types
Grant 9,952,874 - Barrick , et al. April 24, 2 | 2018-04-24 |
Split-level history buffer in a computer processing unit
Grant 9,940,139 - Le , et al. April 10, 2 | 2018-04-10 |
Ecc Scrubbing Method In A Multi-slice Microprocessor
App 20180095820 - Barrick; Brian D. ; et al. | 2018-04-05 |
Reducing Power Consumption In A Multi-slice Computer Processor
App 20180088653 - BATTLE; STEVEN J. ; et al. | 2018-03-29 |
In-pipe error scrubbing within a processor core
Grant 9,928,128 - Barrick , et al. March 27, 2 | 2018-03-27 |
Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor
Grant 9,928,073 - Bowman , et al. March 27, 2 | 2018-03-27 |
Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor
Grant 9,921,833 - Bowman , et al. March 20, 2 | 2018-03-20 |
Reducing Power Consumption In A Multi-slice Computer Processor
App 20180074565 - BATTLE; STEVEN J. ; et al. | 2018-03-15 |
Independent Mapping Of Threads
App 20180067746 - Chu; Sam G. ; et al. | 2018-03-08 |
Age based fast instruction issue
Grant 9,880,850 - Brownscheidle , et al. January 30, 2 | 2018-01-30 |
Reducing power consumption in a multi-slice computer processor
Grant 9,870,039 - Battle , et al. January 16, 2 | 2018-01-16 |
Reducing power consumption in a multi-slice computer processor
Grant 9,870,045 - Battle , et al. January 16, 2 | 2018-01-16 |
Independent mapping of threads
Grant 9,870,229 - Chu , et al. January 16, 2 | 2018-01-16 |
Age based fast instruction issue
Grant 9,870,231 - Brownscheidle , et al. January 16, 2 | 2018-01-16 |
Operation Of A Multi-slice Processor Implementing Prioritized Dependency Chain Resolution
App 20180004527 - ADEEB; KHANDKER N. ; et al. | 2018-01-04 |
Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor
Grant 9,858,078 - Bowman , et al. January 2, 2 | 2018-01-02 |
Split-level history buffer in a computer processing unit
Grant 9,851,979 - Le , et al. December 26, 2 | 2017-12-26 |
Operation Of A Multi-slice Processor Implementing Dependency Accumulation Instruction Sequencing
App 20170364358 - ADEEB; KHANDKER N. ; et al. | 2017-12-21 |
Techniques For Implementing Store Instructions In A Multi-slice Processor Architecture
App 20170364356 - AYUB; SALMA ; et al. | 2017-12-21 |
ECC scrubbing in a multi-slice microprocessor
Grant 9,846,614 - Barrick , et al. December 19, 2 | 2017-12-19 |
Transmitting Data Between Execution Slices Of A Multi-slice Processor
App 20170357513 - AYUB; SALMA ; et al. | 2017-12-14 |
Ecc Scrubbing In A Multi-slice Microprocessor
App 20170351568 - BARRICK; Brian D. ; et al. | 2017-12-07 |
Operation Of A Multi-slice Processor Implementing Adaptive Failure State Capture
App 20170351583 - ADEEB; KHANDKER N. ; et al. | 2017-12-07 |
Operation Of A Multi-slice Processor Implementing Load-hit-store Handling
App 20170351522 - AYUB; SALMA ; et al. | 2017-12-07 |
Direct Register Restore Mechanism For Distributed History Buffers
App 20170344380 - BARRICK; Brian D. ; et al. | 2017-11-30 |
Age Based Fast Instruction Issue
App 20170322812 - Brownscheidle; Jeffrey C. ; et al. | 2017-11-09 |
Merging Status And Control Data In A Reservation Station
App 20170315528 - Barrick; Brian ; et al. | 2017-11-02 |
Adaptive Debug Tracing For Microprocessors
App 20170308454 - ADEEB; Khandker N. ; et al. | 2017-10-26 |
Fpscr Sticky Bit Handling For Out Of Order Instruction Execution
App 20170300336 - BARRICK; BRIAN D. ; et al. | 2017-10-19 |
Thread Transition Management
App 20170300331 - Abernathy; Christopher M. ; et al. | 2017-10-19 |
Rotational Dispatch For Parallel Slice Processor
App 20170293488 - Feiste; Kurt A. ; et al. | 2017-10-12 |
Fast Multi-width Instruction Issue In Parallel Slice Processor
App 20170293489 - Ayub; Salma ; et al. | 2017-10-12 |
Operation Of A Multi-slice Processor Implementing A Hardware Level Transfer Of An Execution Thread
App 20170286183 - BARRICK; BRIAN D. ; et al. | 2017-10-05 |
In-pipe Error Scrubbing Within A Processor Core
App 20170286202 - BARRICK; BRIAN D. ; et al. | 2017-10-05 |
Mechanism For Using A Reservation Station As A Scratch Register
App 20170277541 - CHADHA; SUNDEEP ; et al. | 2017-09-28 |
Techniques For Restoring Previous Values To Registers Of A Processor Register File
App 20170277535 - LE; HUNG Q. ; et al. | 2017-09-28 |
Preventing Premature Reads From A General Purpose Register
App 20170269936 - BATTLE; STEVEN J. ; et al. | 2017-09-21 |
Age Based Fast Instruction Issue
App 20170269938 - Brownscheidle; Jeffrey C. ; et al. | 2017-09-21 |
Partial ECC handling for a byte-write capable register
Grant 9,766,975 - Jeganathan , et al. September 19, 2 | 2017-09-19 |
Operation Of A Multi-slice Processor Implementing Dynamic Switching Of Instruction Issuance Order
App 20170255463 - BROWNSCHEIDLE; JEFFREY C. ; et al. | 2017-09-07 |
Distributed history buffer flush and restore handling in a parallel slice design
Grant 9,747,217 - Ayub , et al. August 29, 2 | 2017-08-29 |
Distributed history buffer flush and restore handling in a parallel slice design
Grant 9,740,620 - Ayub , et al. August 22, 2 | 2017-08-22 |
Operation Of A Multi-slice Processor Implementing A Mechanism To Overcome A System Hang
App 20170235577 - BROWNSCHEIDLE; JEFFREY C. ; et al. | 2017-08-17 |
Operation Of A Multi-slice Processor With History Buffers Storing Transaction Memory State Information
App 20170235674 - BARRICK; BRIAN D. ; et al. | 2017-08-17 |
Parallel Dispatching Of Multi-operation Instructions In A Multi-slice Computer Processor
App 20170228234 - FEISTE; KURT A. ; et al. | 2017-08-10 |
Independent mapping of threads
Grant 9,720,696 - Chu , et al. August 1, 2 | 2017-08-01 |
Thread transition management
Grant 9,703,561 - Abernathy , et al. July 11, 2 | 2017-07-11 |
Operation Of A Multi-slice Processor With Speculative Data Loading
App 20170168821 - BOWMAN; JOSHUA W. ; et al. | 2017-06-15 |
Operation Of A Multi-slice Processor With Instruction Queue Processing
App 20170168835 - BARRICK; BRIAN D. ; et al. | 2017-06-15 |
Reducing Power Consumption In A Multi-slice Computer Processor
App 20170168539 - BATTLE; STEVEN J. ; et al. | 2017-06-15 |
Operation Of A Multi-slice Processor With Instruction Queue Processing
App 20170168831 - BARRICK; BRIAN D. ; et al. | 2017-06-15 |
Handling Unaligned Load Operations In A Multi-slice Computer Processor
App 20170168823 - CHADHA; SUNDEEP ; et al. | 2017-06-15 |
Operation Of A Multi-slice Processor With Reduced Flush And Restore Latency
App 20170168826 - AYUB; SALMA ; et al. | 2017-06-15 |
Operation Of A Multi-slice Processor With Selective Producer Instruction Types
App 20170168834 - BARRICK; BRIAN D. ; et al. | 2017-06-15 |
Operation Of A Multi-slice Processor With Selective Producer Instruction Types
App 20170168822 - BARRICK; BRIAN D. ; et al. | 2017-06-15 |
Operation Of A Multi-slice Processor With Speculative Data Loading
App 20170168836 - BOWMAN; JOSHUA W. ; et al. | 2017-06-15 |
Handling Unaligned Load Operations In A Multi-slice Computer Processor
App 20170168945 - CHADHA; SUNDEEP ; et al. | 2017-06-15 |
Reducing Power Consumption In A Multi-slice Computer Processor
App 20170168544 - BATTLE; STEVEN J. ; et al. | 2017-06-15 |
Energy Efficient Source Operand Issue
App 20170168830 - Brownscheidle; Jeffrey C. ; et al. | 2017-06-15 |
Operation Of A Multi-slice Processor With Reduced Flush And Restore Latency
App 20170168818 - AYUB; Salma ; et al. | 2017-06-15 |
Parity protection of a register
Grant 9,639,418 - Bowman , et al. May 2, 2 | 2017-05-02 |
Method And Apparatus For Writing A Portion Of A Register In A Microprocessor
App 20170109093 - CHU; Sam G. ; et al. | 2017-04-20 |
Method And Apparatus For Managing A Speculative Transaction In A Processing Unit
App 20170109168 - AYUB; Salma ; et al. | 2017-04-20 |
Method And Apparatus For Restoring Data To A Register File Of A Processing Unit
App 20170109167 - EISEN; Susan E. ; et al. | 2017-04-20 |
Method And Apparatus For Processing Instructions In A Microprocessor Having A Multi-execution Slice Architecture
App 20170109171 - EISEN; Susan E. ; et al. | 2017-04-20 |
Method And Apparatus For Recovery In A Microprocessor Having A Multi-execution Slice Architecture
App 20170109166 - EISEN; Susan E. ; et al. | 2017-04-20 |
Efficiently Managing Speculative Finish Tracking And Error Handling For Load Instructions
App 20170090937 - EISEN; SUSAN E. ; et al. | 2017-03-30 |
Efficiently Managing Speculative Finish Tracking And Error Handling For Load Instructions
App 20170090941 - EISEN; SUSAN E. ; et al. | 2017-03-30 |
Parity Protection Of A Register
App 20170060673 - Bowman; Joshua W. ; et al. | 2017-03-02 |
Generating Ecc Values For Byte-write Capable Registers
App 20170060679 - JEGANATHAN; Dhivya ; et al. | 2017-03-02 |
Generating Ecc Values For Byte-write Capable Registers
App 20170060677 - JEGANATHAN; Dhivya ; et al. | 2017-03-02 |
Partial Ecc Mechanism For A Byte-write Capable Register
App 20170063401 - JEGANATHAN; Dhivya ; et al. | 2017-03-02 |
Partial Ecc Handling For A Byte-write Capable Register
App 20170060678 - JEGANATHAN; Dhivya ; et al. | 2017-03-02 |
Age Based Fast Instruction Issue
App 20170031686 - Brownscheidle; Jeffrey C. ; et al. | 2017-02-02 |
Variable Latency Pipe For Interleaving Instruction Tags In A Microprocessor
App 20170003969 - AYUB; Salma ; et al. | 2017-01-05 |
Variable Latency Pipe For Interleaving Instruction Tags In A Microprocessor
App 20170003971 - Ayub; Salma ; et al. | 2017-01-05 |
Techniques To Wake-up Dependent Instructions For Back-to-back Issue In A Microprocessor
App 20160378503 - BROWNSCHEIDLE; Jeffrey C. ; et al. | 2016-12-29 |
Split-level History Buffer In A Computer Processing Unit
App 20160378500 - Le; Hung Q. ; et al. | 2016-12-29 |
Split-level History Buffer In A Computer Processing Unit
App 20160378501 - Le; Hung Q. ; et al. | 2016-12-29 |
Techniques To Wake-up Dependent Instructions For Back-to-back Issue In A Microprocessor
App 20160378504 - BROWNSCHEIDLE; Jeffrey C. ; et al. | 2016-12-29 |
Split-level History Buffer In A Computer Processing Unit
App 20160371087 - Le; Hung Q. ; et al. | 2016-12-22 |
Techniques For Improving Issue Of Instructions With Variable Latencies In A Microprocessor
App 20160371090 - Brownscheidle; Jeffrey C. ; et al. | 2016-12-22 |
Split-level History Buffer In A Computer Processing Unit
App 20160371088 - Le; Hung Q. ; et al. | 2016-12-22 |
Techniques For Improving Issue Of Instructions With Variable Latencies In A Microprocessor
App 20160371091 - BROWNSCHEIDLE; Jeffrey C. ; et al. | 2016-12-22 |
Split-level history buffer in a computer processing unit
Grant 9,524,171 - Le , et al. December 20, 2 | 2016-12-20 |
Speculative Load Data in Byte-Write Capable Register File and History Buffer for a Multi-Slice Microprocessor
App 20160357567 - Bowman; Joshua W. ; et al. | 2016-12-08 |
Speculative Load Data in Byte-Write Capable Register File and History Buffer for a Multi-Slice Microprocessor
App 20160357566 - Bowman; Joshua W. ; et al. | 2016-12-08 |
Distributed History Buffer Flush and Restore Handling in a Parallel Slice Design
App 20160328329 - Ayub; Salma ; et al. | 2016-11-10 |
Distributed History Buffer Flush and Restore Handling in a Parallel Slice Design
App 20160328330 - Ayub; Salma ; et al. | 2016-11-10 |
Processor and method for partially flushing a dispatched instruction group including a mispredicted branch
Grant 9,489,207 - Burky , et al. November 8, 2 | 2016-11-08 |
History Buffer with Single Snoop Tag for Multiple-Field Registers
App 20160283236 - Genden; Michael J. ; et al. | 2016-09-29 |
History Buffer for Multiple-Field Registers
App 20160253181 - Chadha; Sundeep ; et al. | 2016-09-01 |
Universal History Buffer to Support Multiple Register Types
App 20160253177 - Genden; Michael J. ; et al. | 2016-09-01 |
History Buffer with Hybrid Entry Support for Multiple-Field Registers
App 20160253180 - Genden; Michael J. ; et al. | 2016-09-01 |
Speculative finish of instruction execution in a processor core
Grant 9,389,867 - Chadha , et al. July 12, 2 | 2016-07-12 |
Age based fast instruction issue
Grant 9,389,870 - Brownscheidle , et al. July 12, 2 | 2016-07-12 |
Speculative finish of instruction execution in a processor core
Grant 9,384,002 - Chadha , et al. July 5, 2 | 2016-07-05 |
Age based fast instruction issue
Grant 9,367,322 - Brownscheidle , et al. June 14, 2 | 2016-06-14 |
Efficient Usage Of A Multi-level Register File Utilizing A Register File Bypass
App 20160154650 - Abernathy; Christopher M. ; et al. | 2016-06-02 |
Independent Mapping Of Threads
App 20160092276 - Chu; Sam G. ; et al. | 2016-03-31 |
Independent Mapping Of Threads
App 20160092231 - Chu; Sam G. ; et al. | 2016-03-31 |
Efficient usage of a multi-level register file utilizing a register file bypass
Grant 9,286,068 - Abernathy , et al. March 15, 2 | 2016-03-15 |
Speculative Finish Of Instruction Execution In A Processor Core
App 20150370573 - CHADHA; SUNDEEP ; et al. | 2015-12-24 |
Instruction tracking system for processors
Grant 8,874,880 - Abernathy , et al. October 28, 2 | 2014-10-28 |
Thread Transition Management
App 20140258691 - Abernathy; Christopher M. ; et al. | 2014-09-11 |
Speculative Finish Of Instruction Execution In A Processor Core
App 20140143523 - CHADHA; SUNDEEP ; et al. | 2014-05-22 |
Thread transition management
Grant 8,725,993 - Abernathy , et al. May 13, 2 | 2014-05-13 |
Efficient Usage Of A Register File Mapper Mapping Structure
App 20140122842 - Abernathy; Christopher M. ; et al. | 2014-05-01 |
Efficient Usage Of A Multi-level Register File Utilizing A Register File Bypass
App 20140122840 - Abernathy; Christopher M. ; et al. | 2014-05-01 |
Efficient Usage Of A Register File Mapper And First-level Data Register File
App 20140122841 - Abernathy; Christopher M. ; et al. | 2014-05-01 |
Multi-level register file supporting multiple threads
Grant 8,661,227 - Abernathy , et al. February 25, 2 | 2014-02-25 |
Multi-level register file supporting multiple threads
Grant 8,661,228 - Abernathy , et al. February 25, 2 | 2014-02-25 |
Register file supporting transactional processing
Grant 8,631,223 - Abernathy , et al. January 14, 2 | 2014-01-14 |
Instruction Tracking System For Processors
App 20130346731 - Abernathy; Christopher M. ; et al. | 2013-12-26 |
Speeding Up Younger Store Instruction Execution after a Sync Instruction
App 20130305022 - Eisen; Susan E. ; et al. | 2013-11-14 |
Completion arbitration for more than two threads based on resource limitations
Grant 8,386,753 - Eisen , et al. February 26, 2 | 2013-02-26 |
Thread Transition Management
App 20120216004 - Abernathy; Christopher M. ; et al. | 2012-08-23 |
Multi-level Register File Supporting Multiple Threads
App 20120204009 - ABERNATHY; CHRISTOPHER M. ; et al. | 2012-08-09 |
Enhanced load lookahead prefetch in single threaded mode for a simultaneous multithreaded microprocessor
Grant 8,145,887 - Le , et al. March 27, 2 | 2012-03-27 |
Multi-level Register File Supporting Multiple Threads
App 20120072700 - ABERNATHY; CHRISTOPHER M. ; et al. | 2012-03-22 |
Instruction Tracking System For Processors
App 20110302392 - Abernathy; Christopher M. ; et al. | 2011-12-08 |
Register File Supporting Transactional Processing
App 20110283096 - ABERNATHY; CHRISTOPHER M. ; et al. | 2011-11-17 |
Issuing instructions in-order in an out-of-order processor using false dependencies
Grant 8,037,366 - Abernathy , et al. October 11, 2 | 2011-10-11 |
Adaptive allocation of reservation station entries to an instruction set with variable operands in a microprocessor
Grant 7,979,677 - Nguyen July 12, 2 | 2011-07-12 |
Enhanced single threaded execution in a simultaneous multithreaded microprocessor
Grant 7,827,389 - Le , et al. November 2, 2 | 2010-11-02 |
Partial Flush Handling with Multiple Branches Per Group
App 20100262807 - Burky; William E. ; et al. | 2010-10-14 |
Completion Arbitration for More than Two Threads Based on Resource Limitations
App 20100262967 - Eisen; Susan E. ; et al. | 2010-10-14 |
Dependency Matrix with Improved Performance
App 20100257339 - Brown; Mary D. ; et al. | 2010-10-07 |
Selective Execution Dependency Matrix
App 20100257341 - Brown; Mary D. ; et al. | 2010-10-07 |
Universal register rename mechanism for instructions with multiple targets in a microprocessor
Grant 7,809,929 - Le , et al. October 5, 2 | 2010-10-05 |
Issuing Instructions In-Order in an Out-of-Order Processor Using False Dependencies
App 20100251016 - Abernathy; Christopher M. ; et al. | 2010-09-30 |
System and method for implementing a software-supported thread assist mechanism for a microprocessor
Grant 7,779,233 - Le , et al. August 17, 2 | 2010-08-17 |
System and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessor
Grant 7,779,234 - Bishop , et al. August 17, 2 | 2010-08-17 |
Universal register rename mechanism for targets of different instruction types in a microprocessor
Grant 7,765,384 - Le , et al. July 27, 2 | 2010-07-27 |
Method and system for restoring register mapper states for an out-of-order microprocessor
Grant 7,689,812 - Abernathy , et al. March 30, 2 | 2010-03-30 |
System and Method for Implementing a Software-Supported Thread Assist Mechanism for a Microprocessor
App 20090106534 - Le; Hung Q. ; et al. | 2009-04-23 |
System and Method for Implementing a Hardware-Supported Thread Assist Under Load Lookahead Mechanism for a Microprocessor
App 20090106538 - Bishop; James W. ; et al. | 2009-04-23 |
Adaptive Allocation Of Reservation Station Entries To An Instruction Set With Variable Operands In A Microprocessor
App 20090037698 - NGUYEN; DUNG Q. | 2009-02-05 |
System for managing data dependency using bit field instruction destination vector identifying destination for execution results
Grant 7,475,226 - Le , et al. January 6, 2 | 2009-01-06 |
Enhanced Single Threaded Execution in a Simultaneous Multithreaded Microprocessor
App 20080313422 - Le; Hung Q. ; et al. | 2008-12-18 |
Enhanced Load Lookahead Prefetch in Single Threaded Mode for a Simultaneous Multithreaded Microprocessor
App 20080313425 - Le; Hung Q. ; et al. | 2008-12-18 |
Universal Register Rename Mechanism for Instructions with Multiple Targets in a Microprocessor
App 20080263331 - Le; Hung Q. ; et al. | 2008-10-23 |
Universal Register Rename Mechanism for Targets of Different Instruction Types in a Microprocessor
App 20080263321 - Le; Hung Q. ; et al. | 2008-10-23 |
Method and System for Restoring Register Mapper States for an Out-Of-Order Microprocessor
App 20080195850 - Abernathy; Christopher M. ; et al. | 2008-08-14 |
Dynamic recalculation of resource vector at issue queue for steering of dependent instructions
Grant 7,395,414 - Le , et al. July 1, 2 | 2008-07-01 |
Dynamic Recalculation Of Resource Vector At Issue Queue For Steering Of Dependent Instructions
App 20080133890 - Le; Hung Q. ; et al. | 2008-06-05 |
Data Processing System, Processor And Method Of Data Processing Employing An Improved Instruction Destination Tag
App 20080072018 - Le; Hung Q. ; et al. | 2008-03-20 |
Completion table configured to track a larger number of outstanding instructions without increasing the size of the completion table
Grant 7,278,011 - Eisen , et al. October 2, 2 | 2007-10-02 |
Method and circuit for reading and writing an instruction buffer
Grant 7,243,170 - Buti , et al. July 10, 2 | 2007-07-10 |
SMT flush arbitration
Grant 7,194,603 - Burky , et al. March 20, 2 | 2007-03-20 |
Method and apparatus for dynamic modification of microprocessor instruction group at dispatch
App 20060184768 - Bishop; James W. ; et al. | 2006-08-17 |
Dynamic recalculation of resource vector at issue queue for steering of dependent instructions
App 20060184767 - Le; Hung Q. ; et al. | 2006-08-17 |
Register rename array with individual thread bits set upon allocation and cleared upon instruction completion
Grant 7,093,106 - Ambekar , et al. August 15, 2 | 2006-08-15 |
Completion table configured to track a larger number of outstanding instructions
App 20050228972 - Eisen, Susan E. ; et al. | 2005-10-13 |
Method And Circuit For Reading And Writing An Instruction Buffer
App 20050114603 - Buti, Taqi N. ; et al. | 2005-05-26 |
Method and circuit for using a single rename array in a simultaneous multithread system
App 20040215936 - Ambekar, Asit S. ; et al. | 2004-10-28 |
SMT flush arbitration
App 20040215938 - Burky, William E. ; et al. | 2004-10-28 |
Mechanism to assign more logical load/store tags than available physical registers in a microprocessor system
App 20030182537 - Le, Hung Q. ; et al. | 2003-09-25 |
Fetch and store buffer that enables out-of-order execution of memory instructions in a data processing system
Grant 5,465,336 - Imai , et al. November 7, 1 | 1995-11-07 |
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